Implementation of combinational logic gates

To implement the given logic function verify its operation in Quartus using Verilog programming. F1= A’B’C’D’+AC’D’+B’CD’+A’BCD+BC’D F2=xy’z+x’y’z+w’xy+wx’y+wxy

Program to implement the given logic function and to verify its operations in quartus using Verilog programming. Developed by: MADHANRAJ P RegisterNumber: 23013616

module ex_02(a,b,c,d,f1); input a,b,c,d; output f1; wire x1,x2,x3,x4,x5; assign x1=(~a)&(~b)&(~c)&(~d); assign x2=(a) &(~c)&(~d); assign x3=(~b)& (c) &(~d); assign x4=(~a)& (b) & (c) & (d); assign x5=(b) & (~c)&(d); assign f1=x1|x2|x3|x4|x5; endmodule

Thus the given logic functions are implemented using and their operations are verified using Verilog programming.