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View Code? Open in Web Editor NEWMacro assembler for Broadcom VideoCore IV aka Raspberry Pi GPU
License: Other
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fran6co byteit101 jackokring msperl lifengliu yggdrasii doe300 greenpdx develone moneytech pkoenig10 senjienly jimmykenmerchant long-long-float ramtej seanreichle ziqi-zhangvc4asm's Issues
Concerns regarding documentation addendum about branch distance
When trying to use the dynamic semaphore acquisition snippet from the "Addendum to the Broadcom VideoCore IV documentation" page I encountered two problems. The first is this:
mul24 ra31, r0, 3*8 cannot be encoded since 24 doesn't fit in the small immediates field, so an extra mov or ldi is needed before this line.
The second problem might be of my own doing, but so far it has appeared to me that it's only ever possible to make these 'rapid branches' if the conditions for the two branches are mutually exclusive. I've tried a few changes to the code provided in the documentation, but no matter what I do it simply crashes for me. Putting the second branch on the first line of each of the sub-blocks (and changing 3*8 to 4*8) fixes it for me. I have succesfully used a rapid branch with mutually exclusive conditions elsewhere, though.
Cannot build with new Makefile on macOS
Attempting to build V0.2.3 fails on macOS due to the changes made in #15. The old Makefile still builds successfully.
The error is, as follows:
==> make -C src
mkdir ../obj
g++ -Wall -std=c++11 -g -c -fPIC -o ../obj/utils.o utils.cpp
g++ -Wall -std=c++11 -g -c -fPIC -o ../obj/Message.o Message.cpp
g++ -Wall -std=c++11 -g -c -fPIC -o ../obj/expr.o expr.cpp
g++ -Wall -std=c++11 -g -c -fPIC -o ../obj/Inst.o Inst.cpp
g++ -Wall -std=c++11 -g -c -fPIC -o ../obj/Eval.o Eval.cpp
g++ -Wall -std=c++11 -g -c -fPIC -o ../obj/Validator.o Validator.cpp
g++ -Wall -std=c++11 -g -c -fPIC -o ../obj/AssembleInst.o AssembleInst.cpp
g++ -Wall -std=c++11 -g -c -fPIC -o ../obj/Parser.o Parser.cpp
g++ -Wall -std=c++11 -g -c -fPIC -o ../obj/vc4asm.o vc4asm.cpp
g++ -Wall -std=c++11 -g -c -fPIC -o ../obj/WriteELF.o WriteELF.cpp
gcc -Wall -std=c++11 -g -o ../bin/vc4asm ../obj/utils.o ../obj/Message.o ../obj/expr.o ../obj/Inst.o ../obj/Eval.o ../obj/Validator.o ../obj/AssembleInst.o ../obj/Parser.o ../obj/vc4asm.o ../obj/WriteELF.o -lm -lstdc++
g++ -Wall -std=c++11 -g -c -fPIC -o ../obj/Disassembler.o Disassembler.cpp
g++ -Wall -std=c++11 -g -c -fPIC -o ../obj/vc4dis.o vc4dis.cpp
gcc -Wall -std=c++11 -g -o ../bin/vc4dis ../obj/utils.o ../obj/Message.o ../obj/expr.o ../obj/Inst.o ../obj/Eval.o ../obj/Validator.o ../obj/Disassembler.o ../obj/vc4dis.o -lm -lstdc++
mkdir ../lib
ar rcs -o ../lib/libvc4asm.a ../obj/utils.o ../obj/Message.o ../obj/expr.o ../obj/Inst.o ../obj/Eval.o ../obj/Validator.o ../obj/AssembleInst.o ../obj/Parser.o ../obj/WriteELF.o ../obj/Disassembler.o
ar: illegal option combination for -r
usage: ar -d [-TLsv] archive file ...
ar -m [-TLsv] archive file ...
ar -m [-abiTLsv] position archive file ...
ar -p [-TLsv] archive [file ...]
ar -q [-cTLsv] archive file ...
ar -r [-cuTLsv] archive file ...
ar -r [-abciuTLsv] position archive file ...
ar -t [-TLsv] archive [file ...]
ar -x [-ouTLsv] archive [file ...]
make: *** [../lib/libvc4asm.a] Error 1
/usr/local/Homebrew/Library/Homebrew/debrew.rb:11:in `raise'
Add a license (to asm include files)
I am using the file "vc4.inc" in my project, but without a license, I am technically not allowed to include it at all, which I only thought of now. I think at least the include files, that are expected to be included in other projects, deserve a license, if not the whole assembler. Also, if possible, one that isn't GPL, as that would infect any project using it (and would prevent me from using it, too, as I am using the MPL license).
Thank you for considering!
Simple test is failing
I'm getting this error when trying to compile the simple test, it seems an easy fix but I don't have the time to check it out:
ERROR: /mnt/c/Users/franc/Code/vc4asm/sample/simple/smitest.qasm (77,41): Invalid operator: &-
ERROR: /mnt/c/Users/franc/Code/vc4asm/sample/simple/smitest.qasm (78,74): Invalid operator: &-
ERROR: /mnt/c/Users/franc/Code/vc4asm/sample/simple/smitest.qasm (147,42): Invalid operator: &-
ERROR: /mnt/c/Users/franc/Code/vc4asm/sample/simple/smitest.qasm (148,76): Invalid operator: &-
Missing cmath
Fedora 23 with GCC 6 reports fabs, ::isinf and INFINITY as not defined.
This can be solved by including <cmath> or math.h in the cpp-files in question.
Sample programs on current Raspbian fails
Hello,
I'm using a RPi B with Raspbian (latest rpi-update updates the kernel to
Linux raspberrypi 4.1.6+ #810 PREEMPT Tue Aug 18 15:19:58 BST 2015 armv6l GNU/Linux ) and compiling your code with gcc version 4.8.2 (Raspbian 4.8.2-21~rpi3rpi1).
Unfortunately I can not reproduce your results with the hello_fft sample. I do not know if the output indicates a problem during the assembling step. The compiling didn't produce any warnings.
Did the current commit still running on your system? Should I try an other compiler or does you had an other idea?
Your kernel module vcio2 wasn't used.
Regards Yggdrasil
[...]/vc4asm/sample/hello_fft$ sudo ./profile.pl
8 1 20 ... drop 10, avg = 19, median = 19, dev. = 0 = 0%
9 1 20 ... drop 2, avg = 30.7059, median = 31, dev. = 0 = 0%
10 1 20 ... drop 0, avg = 47.1053, median = 47, dev. = 0 = 0%
11 1 20 ... drop 2, avg = 89.4118, median = 89, dev. = 0 = 0%
12 1 20 ... drop 1, avg = 233.056, median = 233, dev. = 0 = 0%
13 1 20 ... drop 0, avg = 631.316, median = 631, dev. = 1 = 0.16%
14 1 20 ... drop 0, avg = 1274.32, median = 1275, dev. = 1 = 0.078%
15 1 20 ... drop 0, avg = 2749.89, median = 2753, dev. = 1 = 0.036%
16 1 20 ... drop 0, avg = 5396.47, median = 5391, dev. = 4 = 0.074%
17 1 20 ... RMS error out of range: rel_rms_err = 1.69325e+02, usecs = 5182.000000, k = 1
RMS error out of range: rel_rms_err = 1.75268e+02, usecs = 5190.000000, k = 2
RMS error out of range: rel_rms_err = 1.69325e+02, usecs = 5204.000000, k = 3
[...]
The other sample program produces
vc4asm/sample/simple$ sudo ./smitest
Exec: 80000000
A 0 0x00000000 0
B 0 0x00000000 0
fadd -1145324613 0xbbbbbbbb -0.00572917
fsub -1145324613 0xbbbbbbbb -0.00572917
fmin -1145324613 0xbbbbbbbb -0.00572917
fmax -1145324613 0xbbbbbbbb -0.00572917
fminabs -1145324613 0xbbbbbbbb -0.00572917
fmaxabs -1145324613 0xbbbbbbbb -0.00572917
ftoi -1145324613 0xbbbbbbbb -0.00572917
itof -1145324613 0xbbbbbbbb -0.00572917
add -1145324613 0xbbbbbbbb -0.00572917
sub -1145324613 0xbbbbbbbb -0.00572917
shr -1145324613 0xbbbbbbbb -0.00572917
asr -1145324613 0xbbbbbbbb -0.00572917
ror -1145324613 0xbbbbbbbb -0.00572917
shl -1145324613 0xbbbbbbbb -0.00572917
min -1145324613 0xbbbbbbbb -0.00572917
max -1145324613 0xbbbbbbbb -0.00572917
and -1145324613 0xbbbbbbbb -0.00572917
or -1145324613 0xbbbbbbbb -0.00572917
xor -1145324613 0xbbbbbbbb -0.00572917
not -1145324613 0xbbbbbbbb -0.00572917
clz -1145324613 0xbbbbbbbb -0.00572917
fmul -1145324613 0xbbbbbbbb -0.00572917
mul24 -1145324613 0xbbbbbbbb -0.00572917
v8muld -1145324613 0xbbbbbbbb -0.00572917
v8min -1145324613 0xbbbbbbbb -0.00572917
v8max -1145324613 0xbbbbbbbb -0.00572917
v8adds -1145324613 0xbbbbbbbb -0.00572917
v8subs -1145324613 0xbbbbbbbb -0.00572917
A0 -1145324613 0xbbbbbbbb -0.00572917
A9 -1145324613 0xbbbbbbbb -0.00572917
A10 -1145324613 0xbbbbbbbb -0.00572917
A11 -1145324613 0xbbbbbbbb -0.00572917
A25 -1145324613 0xbbbbbbbb -0.00572917
A26 -1145324613 0xbbbbbbbb -0.00572917
A27 -1145324613 0xbbbbbbbb -0.00572917
A28 -1145324613 0xbbbbbbbb -0.00572917
A29 -1145324613 0xbbbbbbbb -0.00572917
M0 -1145324613 0xbbbbbbbb -0.00572917
A 1 0x00000001 1.4013e-45
B 1 0x00000001 1.4013e-45
fadd -1145324613 0xbbbbbbbb -0.00572917
fsub -1145324613 0xbbbbbbbb -0.00572917
fmin -1145324613 0xbbbbbbbb -0.00572917
fmax -1145324613 0xbbbbbbbb -0.00572917
fminabs -1145324613 0xbbbbbbbb -0.00572917
fmaxabs -1145324613 0xbbbbbbbb -0.00572917
ftoi -1145324613 0xbbbbbbbb -0.00572917
itof -1145324613 0xbbbbbbbb -0.00572917
add -1145324613 0xbbbbbbbb -0.00572917
sub -1145324613 0xbbbbbbbb -0.00572917
shr -1145324613 0xbbbbbbbb -0.00572917
asr -1145324613 0xbbbbbbbb -0.00572917
ror -1145324613 0xbbbbbbbb -0.00572917
shl -1145324613 0xbbbbbbbb -0.00572917
min -1145324613 0xbbbbbbbb -0.00572917
max -1145324613 0xbbbbbbbb -0.00572917
and -1145324613 0xbbbbbbbb -0.00572917
or -1145324613 0xbbbbbbbb -0.00572917
xor -1145324613 0xbbbbbbbb -0.00572917
not -1145324613 0xbbbbbbbb -0.00572917
clz -1145324613 0xbbbbbbbb -0.00572917
fmul -1145324613 0xbbbbbbbb -0.00572917
mul24 -1145324613 0xbbbbbbbb -0.00572917
v8muld -1145324613 0xbbbbbbbb -0.00572917
v8min -1145324613 0xbbbbbbbb -0.00572917
v8max -1145324613 0xbbbbbbbb -0.00572917
v8adds -1145324613 0xbbbbbbbb -0.00572917
v8subs -1145324613 0xbbbbbbbb -0.00572917
A0 -1145324613 0xbbbbbbbb -0.00572917
A9 -1145324613 0xbbbbbbbb -0.00572917
A10 -1145324613 0xbbbbbbbb -0.00572917
A11 -1145324613 0xbbbbbbbb -0.00572917
A25 -1145324613 0xbbbbbbbb -0.00572917
A26 -1145324613 0xbbbbbbbb -0.00572917
A27 -1145324613 0xbbbbbbbb -0.00572917
A28 -1145324613 0xbbbbbbbb -0.00572917
A29 -1145324613 0xbbbbbbbb -0.00572917
M0 -1145324613 0xbbbbbbbb -0.00572917
A 2 0x00000002 2.8026e-45
B 2 0x00000002 2.8026e-45
fadd -1145324613 0xbbbbbbbb -0.00572917
fsub -1145324613 0xbbbbbbbb -0.00572917
fmin -1145324613 0xbbbbbbbb -0.00572917
fmax -1145324613 0xbbbbbbbb -0.00572917
fminabs -1145324613 0xbbbbbbbb -0.00572917
fmaxabs -1145324613 0xbbbbbbbb -0.00572917
ftoi -1145324613 0xbbbbbbbb -0.00572917
itof -1145324613 0xbbbbbbbb -0.00572917
add -1145324613 0xbbbbbbbb -0.00572917
sub -1145324613 0xbbbbbbbb -0.00572917
shr -1145324613 0xbbbbbbbb -0.00572917
asr -1145324613 0xbbbbbbbb -0.00572917
ror -1145324613 0xbbbbbbbb -0.00572917
shl -1145324613 0xbbbbbbbb -0.00572917
min -1145324613 0xbbbbbbbb -0.00572917
max -1145324613 0xbbbbbbbb -0.00572917
and -1145324613 0xbbbbbbbb -0.00572917
or -1145324613 0xbbbbbbbb -0.00572917
xor -1145324613 0xbbbbbbbb -0.00572917
not -1145324613 0xbbbbbbbb -0.00572917
clz -1145324613 0xbbbbbbbb -0.00572917
fmul -1145324613 0xbbbbbbbb -0.00572917
mul24 -1145324613 0xbbbbbbbb -0.00572917
v8muld -1145324613 0xbbbbbbbb -0.00572917
v8min -1145324613 0xbbbbbbbb -0.00572917
v8max -1145324613 0xbbbbbbbb -0.00572917
v8adds -1145324613 0xbbbbbbbb -0.00572917
v8subs -1145324613 0xbbbbbbbb -0.00572917
A0 -1145324613 0xbbbbbbbb -0.00572917
A9 -1145324613 0xbbbbbbbb -0.00572917
A10 -1145324613 0xbbbbbbbb -0.00572917
A11 -1145324613 0xbbbbbbbb -0.00572917
A25 -1145324613 0xbbbbbbbb -0.00572917
A26 -1145324613 0xbbbbbbbb -0.00572917
A27 -1145324613 0xbbbbbbbb -0.00572917
A28 -1145324613 0xbbbbbbbb -0.00572917
A29 -1145324613 0xbbbbbbbb -0.00572917
M0 -1145324613 0xbbbbbbbb -0.00572917
A 3 0x00000003 4.2039e-45
B 3 0x00000003 4.2039e-45
fadd -1145324613 0xbbbbbbbb -0.00572917
fsub -1145324613 0xbbbbbbbb -0.00572917
fmin -1145324613 0xbbbbbbbb -0.00572917
fmax -1145324613 0xbbbbbbbb -0.00572917
fminabs -1145324613 0xbbbbbbbb -0.00572917
fmaxabs -1145324613 0xbbbbbbbb -0.00572917
ftoi -1145324613 0xbbbbbbbb -0.00572917
itof -1145324613 0xbbbbbbbb -0.00572917
add -1145324613 0xbbbbbbbb -0.00572917
sub -1145324613 0xbbbbbbbb -0.00572917
shr -1145324613 0xbbbbbbbb -0.00572917
asr -1145324613 0xbbbbbbbb -0.00572917
ror -1145324613 0xbbbbbbbb -0.00572917
shl -1145324613 0xbbbbbbbb -0.00572917
min -1145324613 0xbbbbbbbb -0.00572917
max -1145324613 0xbbbbbbbb -0.00572917
and -1145324613 0xbbbbbbbb -0.00572917
or -1145324613 0xbbbbbbbb -0.00572917
xor -1145324613 0xbbbbbbbb -0.00572917
not -1145324613 0xbbbbbbbb -0.00572917
clz -1145324613 0xbbbbbbbb -0.00572917
fmul -1145324613 0xbbbbbbbb -0.00572917
mul24 -1145324613 0xbbbbbbbb -0.00572917
v8muld -1145324613 0xbbbbbbbb -0.00572917
v8min -1145324613 0xbbbbbbbb -0.00572917
v8max -1145324613 0xbbbbbbbb -0.00572917
v8adds -1145324613 0xbbbbbbbb -0.00572917
v8subs -1145324613 0xbbbbbbbb -0.00572917
A0 -1145324613 0xbbbbbbbb -0.00572917
A9 -1145324613 0xbbbbbbbb -0.00572917
A10 -1145324613 0xbbbbbbbb -0.00572917
A11 -1145324613 0xbbbbbbbb -0.00572917
A25 -1145324613 0xbbbbbbbb -0.00572917
A26 -1145324613 0xbbbbbbbb -0.00572917
A27 -1145324613 0xbbbbbbbb -0.00572917
A28 -1145324613 0xbbbbbbbb -0.00572917
A29 -1145324613 0xbbbbbbbb -0.00572917
M0 -1145324613 0xbbbbbbbb -0.00572917
A 4 0x00000004 5.60519e-45
B 4 0x00000004 5.60519e-45
fadd -1145324613 0xbbbbbbbb -0.00572917
fsub -1145324613 0xbbbbbbbb -0.00572917
fmin -1145324613 0xbbbbbbbb -0.00572917
fmax -1145324613 0xbbbbbbbb -0.00572917
fminabs -1145324613 0xbbbbbbbb -0.00572917
fmaxabs -1145324613 0xbbbbbbbb -0.00572917
ftoi -1145324613 0xbbbbbbbb -0.00572917
itof -1145324613 0xbbbbbbbb -0.00572917
add -1145324613 0xbbbbbbbb -0.00572917
sub -1145324613 0xbbbbbbbb -0.00572917
shr -1145324613 0xbbbbbbbb -0.00572917
asr -1145324613 0xbbbbbbbb -0.00572917
ror -1145324613 0xbbbbbbbb -0.00572917
shl -1145324613 0xbbbbbbbb -0.00572917
min -1145324613 0xbbbbbbbb -0.00572917
max -1145324613 0xbbbbbbbb -0.00572917
and -1145324613 0xbbbbbbbb -0.00572917
or -1145324613 0xbbbbbbbb -0.00572917
xor -1145324613 0xbbbbbbbb -0.00572917
not -1145324613 0xbbbbbbbb -0.00572917
clz -1145324613 0xbbbbbbbb -0.00572917
fmul -1145324613 0xbbbbbbbb -0.00572917
mul24 -1145324613 0xbbbbbbbb -0.00572917
v8muld -1145324613 0xbbbbbbbb -0.00572917
v8min -1145324613 0xbbbbbbbb -0.00572917
v8max -1145324613 0xbbbbbbbb -0.00572917
v8adds -1145324613 0xbbbbbbbb -0.00572917
v8subs -1145324613 0xbbbbbbbb -0.00572917
A0 -1145324613 0xbbbbbbbb -0.00572917
A9 -1145324613 0xbbbbbbbb -0.00572917
A10 -1145324613 0xbbbbbbbb -0.00572917
A11 -1145324613 0xbbbbbbbb -0.00572917
A25 -1145324613 0xbbbbbbbb -0.00572917
A26 -1145324613 0xbbbbbbbb -0.00572917
A27 -1145324613 0xbbbbbbbb -0.00572917
A28 -1145324613 0xbbbbbbbb -0.00572917
A29 -1145324613 0xbbbbbbbb -0.00572917
M0 -1145324613 0xbbbbbbbb -0.00572917
A 5 0x00000005 7.00649e-45
B 5 0x00000005 7.00649e-45
fadd -1145324613 0xbbbbbbbb -0.00572917
fsub -1145324613 0xbbbbbbbb -0.00572917
fmin -1145324613 0xbbbbbbbb -0.00572917
fmax -1145324613 0xbbbbbbbb -0.00572917
fminabs -1145324613 0xbbbbbbbb -0.00572917
fmaxabs -1145324613 0xbbbbbbbb -0.00572917
ftoi -1145324613 0xbbbbbbbb -0.00572917
itof -1145324613 0xbbbbbbbb -0.00572917
add -1145324613 0xbbbbbbbb -0.00572917
sub -1145324613 0xbbbbbbbb -0.00572917
shr -1145324613 0xbbbbbbbb -0.00572917
asr -1145324613 0xbbbbbbbb -0.00572917
ror -1145324613 0xbbbbbbbb -0.00572917
shl -1145324613 0xbbbbbbbb -0.00572917
min -1145324613 0xbbbbbbbb -0.00572917
max -1145324613 0xbbbbbbbb -0.00572917
and -1145324613 0xbbbbbbbb -0.00572917
or -1145324613 0xbbbbbbbb -0.00572917
xor -1145324613 0xbbbbbbbb -0.00572917
not -1145324613 0xbbbbbbbb -0.00572917
clz -1145324613 0xbbbbbbbb -0.00572917
fmul -1145324613 0xbbbbbbbb -0.00572917
mul24 -1145324613 0xbbbbbbbb -0.00572917
v8muld -1145324613 0xbbbbbbbb -0.00572917
v8min -1145324613 0xbbbbbbbb -0.00572917
v8max -1145324613 0xbbbbbbbb -0.00572917
v8adds -1145324613 0xbbbbbbbb -0.00572917
v8subs -1145324613 0xbbbbbbbb -0.00572917
A0 -1145324613 0xbbbbbbbb -0.00572917
A9 -1145324613 0xbbbbbbbb -0.00572917
A10 -1145324613 0xbbbbbbbb -0.00572917
A11 -1145324613 0xbbbbbbbb -0.00572917
A25 -1145324613 0xbbbbbbbb -0.00572917
A26 -1145324613 0xbbbbbbbb -0.00572917
A27 -1145324613 0xbbbbbbbb -0.00572917
A28 -1145324613 0xbbbbbbbb -0.00572917
A29 -1145324613 0xbbbbbbbb -0.00572917
M0 -1145324613 0xbbbbbbbb -0.00572917
A 6 0x00000006 8.40779e-45
B 6 0x00000006 8.40779e-45
fadd -1145324613 0xbbbbbbbb -0.00572917
fsub -1145324613 0xbbbbbbbb -0.00572917
fmin -1145324613 0xbbbbbbbb -0.00572917
fmax -1145324613 0xbbbbbbbb -0.00572917
fminabs -1145324613 0xbbbbbbbb -0.00572917
fmaxabs -1145324613 0xbbbbbbbb -0.00572917
ftoi -1145324613 0xbbbbbbbb -0.00572917
itof -1145324613 0xbbbbbbbb -0.00572917
add -1145324613 0xbbbbbbbb -0.00572917
sub -1145324613 0xbbbbbbbb -0.00572917
shr -1145324613 0xbbbbbbbb -0.00572917
asr -1145324613 0xbbbbbbbb -0.00572917
ror -1145324613 0xbbbbbbbb -0.00572917
shl -1145324613 0xbbbbbbbb -0.00572917
min -1145324613 0xbbbbbbbb -0.00572917
max -1145324613 0xbbbbbbbb -0.00572917
and -1145324613 0xbbbbbbbb -0.00572917
or -1145324613 0xbbbbbbbb -0.00572917
xor -1145324613 0xbbbbbbbb -0.00572917
not -1145324613 0xbbbbbbbb -0.00572917
clz -1145324613 0xbbbbbbbb -0.00572917
fmul -1145324613 0xbbbbbbbb -0.00572917
mul24 -1145324613 0xbbbbbbbb -0.00572917
v8muld -1145324613 0xbbbbbbbb -0.00572917
v8min -1145324613 0xbbbbbbbb -0.00572917
v8max -1145324613 0xbbbbbbbb -0.00572917
v8adds -1145324613 0xbbbbbbbb -0.00572917
v8subs -1145324613 0xbbbbbbbb -0.00572917
A0 -1145324613 0xbbbbbbbb -0.00572917
A9 -1145324613 0xbbbbbbbb -0.00572917
A10 -1145324613 0xbbbbbbbb -0.00572917
A11 -1145324613 0xbbbbbbbb -0.00572917
A25 -1145324613 0xbbbbbbbb -0.00572917
A26 -1145324613 0xbbbbbbbb -0.00572917
A27 -1145324613 0xbbbbbbbb -0.00572917
A28 -1145324613 0xbbbbbbbb -0.00572917
A29 -1145324613 0xbbbbbbbb -0.00572917
M0 -1145324613 0xbbbbbbbb -0.00572917
A 7 0x00000007 9.80909e-45
B 7 0x00000007 9.80909e-45
fadd -1145324613 0xbbbbbbbb -0.00572917
fsub -1145324613 0xbbbbbbbb -0.00572917
fmin -1145324613 0xbbbbbbbb -0.00572917
fmax -1145324613 0xbbbbbbbb -0.00572917
fminabs -1145324613 0xbbbbbbbb -0.00572917
fmaxabs -1145324613 0xbbbbbbbb -0.00572917
ftoi -1145324613 0xbbbbbbbb -0.00572917
itof -1145324613 0xbbbbbbbb -0.00572917
add -1145324613 0xbbbbbbbb -0.00572917
sub -1145324613 0xbbbbbbbb -0.00572917
shr -1145324613 0xbbbbbbbb -0.00572917
asr -1145324613 0xbbbbbbbb -0.00572917
ror -1145324613 0xbbbbbbbb -0.00572917
shl -1145324613 0xbbbbbbbb -0.00572917
min -1145324613 0xbbbbbbbb -0.00572917
max -1145324613 0xbbbbbbbb -0.00572917
and -1145324613 0xbbbbbbbb -0.00572917
or -1145324613 0xbbbbbbbb -0.00572917
xor -1145324613 0xbbbbbbbb -0.00572917
not -1145324613 0xbbbbbbbb -0.00572917
clz -1145324613 0xbbbbbbbb -0.00572917
fmul -1145324613 0xbbbbbbbb -0.00572917
mul24 -1145324613 0xbbbbbbbb -0.00572917
v8muld -1145324613 0xbbbbbbbb -0.00572917
v8min -1145324613 0xbbbbbbbb -0.00572917
v8max -1145324613 0xbbbbbbbb -0.00572917
v8adds -1145324613 0xbbbbbbbb -0.00572917
v8subs -1145324613 0xbbbbbbbb -0.00572917
A0 -1145324613 0xbbbbbbbb -0.00572917
A9 -1145324613 0xbbbbbbbb -0.00572917
A10 -1145324613 0xbbbbbbbb -0.00572917
A11 -1145324613 0xbbbbbbbb -0.00572917
A25 -1145324613 0xbbbbbbbb -0.00572917
A26 -1145324613 0xbbbbbbbb -0.00572917
A27 -1145324613 0xbbbbbbbb -0.00572917
A28 -1145324613 0xbbbbbbbb -0.00572917
A29 -1145324613 0xbbbbbbbb -0.00572917
M0 -1145324613 0xbbbbbbbb -0.00572917
A 8 0x00000008 1.12104e-44
B 8 0x00000008 1.12104e-44
fadd -1145324613 0xbbbbbbbb -0.00572917
fsub -1145324613 0xbbbbbbbb -0.00572917
fmin -1145324613 0xbbbbbbbb -0.00572917
fmax -1145324613 0xbbbbbbbb -0.00572917
fminabs -1145324613 0xbbbbbbbb -0.00572917
fmaxabs -1145324613 0xbbbbbbbb -0.00572917
ftoi -1145324613 0xbbbbbbbb -0.00572917
itof -1145324613 0xbbbbbbbb -0.00572917
add -1145324613 0xbbbbbbbb -0.00572917
sub -1145324613 0xbbbbbbbb -0.00572917
shr -1145324613 0xbbbbbbbb -0.00572917
asr -1145324613 0xbbbbbbbb -0.00572917
ror -1145324613 0xbbbbbbbb -0.00572917
shl -1145324613 0xbbbbbbbb -0.00572917
min -1145324613 0xbbbbbbbb -0.00572917
max -1145324613 0xbbbbbbbb -0.00572917
and -1145324613 0xbbbbbbbb -0.00572917
or -1145324613 0xbbbbbbbb -0.00572917
xor -1145324613 0xbbbbbbbb -0.00572917
not -1145324613 0xbbbbbbbb -0.00572917
clz -1145324613 0xbbbbbbbb -0.00572917
fmul -1145324613 0xbbbbbbbb -0.00572917
mul24 -1145324613 0xbbbbbbbb -0.00572917
v8muld -1145324613 0xbbbbbbbb -0.00572917
v8min -1145324613 0xbbbbbbbb -0.00572917
v8max -1145324613 0xbbbbbbbb -0.00572917
v8adds -1145324613 0xbbbbbbbb -0.00572917
v8subs -1145324613 0xbbbbbbbb -0.00572917
A0 -1145324613 0xbbbbbbbb -0.00572917
A9 -1145324613 0xbbbbbbbb -0.00572917
A10 -1145324613 0xbbbbbbbb -0.00572917
A11 -1145324613 0xbbbbbbbb -0.00572917
A25 -1145324613 0xbbbbbbbb -0.00572917
A26 -1145324613 0xbbbbbbbb -0.00572917
A27 -1145324613 0xbbbbbbbb -0.00572917
A28 -1145324613 0xbbbbbbbb -0.00572917
A29 -1145324613 0xbbbbbbbb -0.00572917
M0 -1145324613 0xbbbbbbbb -0.00572917
A 9 0x00000009 1.26117e-44
B 9 0x00000009 1.26117e-44
fadd -1145324613 0xbbbbbbbb -0.00572917
fsub -1145324613 0xbbbbbbbb -0.00572917
fmin -1145324613 0xbbbbbbbb -0.00572917
fmax -1145324613 0xbbbbbbbb -0.00572917
fminabs -1145324613 0xbbbbbbbb -0.00572917
fmaxabs -1145324613 0xbbbbbbbb -0.00572917
ftoi -1145324613 0xbbbbbbbb -0.00572917
itof -1145324613 0xbbbbbbbb -0.00572917
add -1145324613 0xbbbbbbbb -0.00572917
sub -1145324613 0xbbbbbbbb -0.00572917
shr -1145324613 0xbbbbbbbb -0.00572917
asr -1145324613 0xbbbbbbbb -0.00572917
ror -1145324613 0xbbbbbbbb -0.00572917
shl -1145324613 0xbbbbbbbb -0.00572917
min -1145324613 0xbbbbbbbb -0.00572917
max -1145324613 0xbbbbbbbb -0.00572917
and -1145324613 0xbbbbbbbb -0.00572917
or -1145324613 0xbbbbbbbb -0.00572917
xor -1145324613 0xbbbbbbbb -0.00572917
not -1145324613 0xbbbbbbbb -0.00572917
clz -1145324613 0xbbbbbbbb -0.00572917
fmul -1145324613 0xbbbbbbbb -0.00572917
mul24 -1145324613 0xbbbbbbbb -0.00572917
v8muld -1145324613 0xbbbbbbbb -0.00572917
v8min -1145324613 0xbbbbbbbb -0.00572917
v8max -1145324613 0xbbbbbbbb -0.00572917
v8adds -1145324613 0xbbbbbbbb -0.00572917
v8subs -1145324613 0xbbbbbbbb -0.00572917
A0 -1145324613 0xbbbbbbbb -0.00572917
A9 -1145324613 0xbbbbbbbb -0.00572917
A10 -1145324613 0xbbbbbbbb -0.00572917
A11 -1145324613 0xbbbbbbbb -0.00572917
A25 -1145324613 0xbbbbbbbb -0.00572917
A26 -1145324613 0xbbbbbbbb -0.00572917
A27 -1145324613 0xbbbbbbbb -0.00572917
A28 -1145324613 0xbbbbbbbb -0.00572917
A29 -1145324613 0xbbbbbbbb -0.00572917
M0 -1145324613 0xbbbbbbbb -0.00572917
A 10 0x0000000a 1.4013e-44
B 10 0x0000000a 1.4013e-44
fadd -1145324613 0xbbbbbbbb -0.00572917
fsub -1145324613 0xbbbbbbbb -0.00572917
fmin -1145324613 0xbbbbbbbb -0.00572917
fmax -1145324613 0xbbbbbbbb -0.00572917
fminabs -1145324613 0xbbbbbbbb -0.00572917
fmaxabs -1145324613 0xbbbbbbbb -0.00572917
ftoi -1145324613 0xbbbbbbbb -0.00572917
itof -1145324613 0xbbbbbbbb -0.00572917
add -1145324613 0xbbbbbbbb -0.00572917
sub -1145324613 0xbbbbbbbb -0.00572917
shr -1145324613 0xbbbbbbbb -0.00572917
asr -1145324613 0xbbbbbbbb -0.00572917
ror -1145324613 0xbbbbbbbb -0.00572917
shl -1145324613 0xbbbbbbbb -0.00572917
min -1145324613 0xbbbbbbbb -0.00572917
max -1145324613 0xbbbbbbbb -0.00572917
and -1145324613 0xbbbbbbbb -0.00572917
or -1145324613 0xbbbbbbbb -0.00572917
xor -1145324613 0xbbbbbbbb -0.00572917
not -1145324613 0xbbbbbbbb -0.00572917
clz -1145324613 0xbbbbbbbb -0.00572917
fmul -1145324613 0xbbbbbbbb -0.00572917
mul24 -1145324613 0xbbbbbbbb -0.00572917
v8muld -1145324613 0xbbbbbbbb -0.00572917
v8min -1145324613 0xbbbbbbbb -0.00572917
v8max -1145324613 0xbbbbbbbb -0.00572917
v8adds -1145324613 0xbbbbbbbb -0.00572917
v8subs -1145324613 0xbbbbbbbb -0.00572917
A0 -1145324613 0xbbbbbbbb -0.00572917
A9 -1145324613 0xbbbbbbbb -0.00572917
A10 -1145324613 0xbbbbbbbb -0.00572917
A11 -1145324613 0xbbbbbbbb -0.00572917
A25 -1145324613 0xbbbbbbbb -0.00572917
A26 -1145324613 0xbbbbbbbb -0.00572917
A27 -1145324613 0xbbbbbbbb -0.00572917
A28 -1145324613 0xbbbbbbbb -0.00572917
A29 -1145324613 0xbbbbbbbb -0.00572917
M0 -1145324613 0xbbbbbbbb -0.00572917
A 11 0x0000000b 1.54143e-44
B 11 0x0000000b 1.54143e-44
fadd -1145324613 0xbbbbbbbb -0.00572917
fsub -1145324613 0xbbbbbbbb -0.00572917
fmin -1145324613 0xbbbbbbbb -0.00572917
fmax -1145324613 0xbbbbbbbb -0.00572917
fminabs -1145324613 0xbbbbbbbb -0.00572917
fmaxabs -1145324613 0xbbbbbbbb -0.00572917
ftoi -1145324613 0xbbbbbbbb -0.00572917
itof -1145324613 0xbbbbbbbb -0.00572917
add -1145324613 0xbbbbbbbb -0.00572917
sub -1145324613 0xbbbbbbbb -0.00572917
shr -1145324613 0xbbbbbbbb -0.00572917
asr -1145324613 0xbbbbbbbb -0.00572917
ror -1145324613 0xbbbbbbbb -0.00572917
shl -1145324613 0xbbbbbbbb -0.00572917
min -1145324613 0xbbbbbbbb -0.00572917
max -1145324613 0xbbbbbbbb -0.00572917
and -1145324613 0xbbbbbbbb -0.00572917
or -1145324613 0xbbbbbbbb -0.00572917
xor -1145324613 0xbbbbbbbb -0.00572917
not -1145324613 0xbbbbbbbb -0.00572917
clz -1145324613 0xbbbbbbbb -0.00572917
fmul -1145324613 0xbbbbbbbb -0.00572917
mul24 -1145324613 0xbbbbbbbb -0.00572917
v8muld -1145324613 0xbbbbbbbb -0.00572917
v8min -1145324613 0xbbbbbbbb -0.00572917
v8max -1145324613 0xbbbbbbbb -0.00572917
v8adds -1145324613 0xbbbbbbbb -0.00572917
v8subs -1145324613 0xbbbbbbbb -0.00572917
A0 -1145324613 0xbbbbbbbb -0.00572917
A9 -1145324613 0xbbbbbbbb -0.00572917
A10 -1145324613 0xbbbbbbbb -0.00572917
A11 -1145324613 0xbbbbbbbb -0.00572917
A25 -1145324613 0xbbbbbbbb -0.00572917
A26 -1145324613 0xbbbbbbbb -0.00572917
A27 -1145324613 0xbbbbbbbb -0.00572917
A28 -1145324613 0xbbbbbbbb -0.00572917
A29 -1145324613 0xbbbbbbbb -0.00572917
M0 -1145324613 0xbbbbbbbb -0.00572917
A 12 0x0000000c 1.68156e-44
B 12 0x0000000c 1.68156e-44
fadd -1145324613 0xbbbbbbbb -0.00572917
fsub -1145324613 0xbbbbbbbb -0.00572917
fmin -1145324613 0xbbbbbbbb -0.00572917
fmax -1145324613 0xbbbbbbbb -0.00572917
fminabs -1145324613 0xbbbbbbbb -0.00572917
fmaxabs -1145324613 0xbbbbbbbb -0.00572917
ftoi -1145324613 0xbbbbbbbb -0.00572917
itof -1145324613 0xbbbbbbbb -0.00572917
add -1145324613 0xbbbbbbbb -0.00572917
sub -1145324613 0xbbbbbbbb -0.00572917
shr -1145324613 0xbbbbbbbb -0.00572917
asr -1145324613 0xbbbbbbbb -0.00572917
ror -1145324613 0xbbbbbbbb -0.00572917
shl -1145324613 0xbbbbbbbb -0.00572917
min -1145324613 0xbbbbbbbb -0.00572917
max -1145324613 0xbbbbbbbb -0.00572917
and -1145324613 0xbbbbbbbb -0.00572917
or -1145324613 0xbbbbbbbb -0.00572917
xor -1145324613 0xbbbbbbbb -0.00572917
not -1145324613 0xbbbbbbbb -0.00572917
clz -1145324613 0xbbbbbbbb -0.00572917
fmul -1145324613 0xbbbbbbbb -0.00572917
mul24 -1145324613 0xbbbbbbbb -0.00572917
v8muld -1145324613 0xbbbbbbbb -0.00572917
v8min -1145324613 0xbbbbbbbb -0.00572917
v8max -1145324613 0xbbbbbbbb -0.00572917
v8adds -1145324613 0xbbbbbbbb -0.00572917
v8subs -1145324613 0xbbbbbbbb -0.00572917
A0 -1145324613 0xbbbbbbbb -0.00572917
A9 -1145324613 0xbbbbbbbb -0.00572917
A10 -1145324613 0xbbbbbbbb -0.00572917
A11 -1145324613 0xbbbbbbbb -0.00572917
A25 -1145324613 0xbbbbbbbb -0.00572917
A26 -1145324613 0xbbbbbbbb -0.00572917
A27 -1145324613 0xbbbbbbbb -0.00572917
A28 -1145324613 0xbbbbbbbb -0.00572917
A29 -1145324613 0xbbbbbbbb -0.00572917
M0 -1145324613 0xbbbbbbbb -0.00572917
A 13 0x0000000d 1.82169e-44
B 13 0x0000000d 1.82169e-44
fadd -1145324613 0xbbbbbbbb -0.00572917
fsub -1145324613 0xbbbbbbbb -0.00572917
fmin -1145324613 0xbbbbbbbb -0.00572917
fmax -1145324613 0xbbbbbbbb -0.00572917
fminabs -1145324613 0xbbbbbbbb -0.00572917
fmaxabs -1145324613 0xbbbbbbbb -0.00572917
ftoi -1145324613 0xbbbbbbbb -0.00572917
itof -1145324613 0xbbbbbbbb -0.00572917
add -1145324613 0xbbbbbbbb -0.00572917
sub -1145324613 0xbbbbbbbb -0.00572917
shr -1145324613 0xbbbbbbbb -0.00572917
asr -1145324613 0xbbbbbbbb -0.00572917
ror -1145324613 0xbbbbbbbb -0.00572917
shl -1145324613 0xbbbbbbbb -0.00572917
min -1145324613 0xbbbbbbbb -0.00572917
max -1145324613 0xbbbbbbbb -0.00572917
and -1145324613 0xbbbbbbbb -0.00572917
or -1145324613 0xbbbbbbbb -0.00572917
xor -1145324613 0xbbbbbbbb -0.00572917
not -1145324613 0xbbbbbbbb -0.00572917
clz -1145324613 0xbbbbbbbb -0.00572917
fmul -1145324613 0xbbbbbbbb -0.00572917
mul24 -1145324613 0xbbbbbbbb -0.00572917
v8muld -1145324613 0xbbbbbbbb -0.00572917
v8min -1145324613 0xbbbbbbbb -0.00572917
v8max -1145324613 0xbbbbbbbb -0.00572917
v8adds -1145324613 0xbbbbbbbb -0.00572917
v8subs -1145324613 0xbbbbbbbb -0.00572917
A0 -1145324613 0xbbbbbbbb -0.00572917
A9 -1145324613 0xbbbbbbbb -0.00572917
A10 -1145324613 0xbbbbbbbb -0.00572917
A11 -1145324613 0xbbbbbbbb -0.00572917
A25 -1145324613 0xbbbbbbbb -0.00572917
A26 -1145324613 0xbbbbbbbb -0.00572917
A27 -1145324613 0xbbbbbbbb -0.00572917
A28 -1145324613 0xbbbbbbbb -0.00572917
A29 -1145324613 0xbbbbbbbb -0.00572917
M0 -1145324613 0xbbbbbbbb -0.00572917
A 14 0x0000000e 1.96182e-44
B 14 0x0000000e 1.96182e-44
fadd -1145324613 0xbbbbbbbb -0.00572917
fsub -1145324613 0xbbbbbbbb -0.00572917
fmin -1145324613 0xbbbbbbbb -0.00572917
fmax -1145324613 0xbbbbbbbb -0.00572917
fminabs -1145324613 0xbbbbbbbb -0.00572917
fmaxabs -1145324613 0xbbbbbbbb -0.00572917
ftoi -1145324613 0xbbbbbbbb -0.00572917
itof -1145324613 0xbbbbbbbb -0.00572917
add -1145324613 0xbbbbbbbb -0.00572917
sub -1145324613 0xbbbbbbbb -0.00572917
shr -1145324613 0xbbbbbbbb -0.00572917
asr -1145324613 0xbbbbbbbb -0.00572917
ror -1145324613 0xbbbbbbbb -0.00572917
shl -1145324613 0xbbbbbbbb -0.00572917
min -1145324613 0xbbbbbbbb -0.00572917
max -1145324613 0xbbbbbbbb -0.00572917
and -1145324613 0xbbbbbbbb -0.00572917
or -1145324613 0xbbbbbbbb -0.00572917
xor -1145324613 0xbbbbbbbb -0.00572917
not -1145324613 0xbbbbbbbb -0.00572917
clz -1145324613 0xbbbbbbbb -0.00572917
fmul -1145324613 0xbbbbbbbb -0.00572917
mul24 -1145324613 0xbbbbbbbb -0.00572917
v8muld -1145324613 0xbbbbbbbb -0.00572917
v8min -1145324613 0xbbbbbbbb -0.00572917
v8max -1145324613 0xbbbbbbbb -0.00572917
v8adds -1145324613 0xbbbbbbbb -0.00572917
v8subs -1145324613 0xbbbbbbbb -0.00572917
A0 -1145324613 0xbbbbbbbb -0.00572917
A9 -1145324613 0xbbbbbbbb -0.00572917
A10 -1145324613 0xbbbbbbbb -0.00572917
A11 -1145324613 0xbbbbbbbb -0.00572917
A25 -1145324613 0xbbbbbbbb -0.00572917
A26 -1145324613 0xbbbbbbbb -0.00572917
A27 -1145324613 0xbbbbbbbb -0.00572917
A28 -1145324613 0xbbbbbbbb -0.00572917
A29 -1145324613 0xbbbbbbbb -0.00572917
M0 -1145324613 0xbbbbbbbb -0.00572917
A 15 0x0000000f 2.10195e-44
B 15 0x0000000f 2.10195e-44
fadd -1145324613 0xbbbbbbbb -0.00572917
fsub -1145324613 0xbbbbbbbb -0.00572917
fmin -1145324613 0xbbbbbbbb -0.00572917
fmax -1145324613 0xbbbbbbbb -0.00572917
fminabs -1145324613 0xbbbbbbbb -0.00572917
fmaxabs -1145324613 0xbbbbbbbb -0.00572917
ftoi -1145324613 0xbbbbbbbb -0.00572917
itof -1145324613 0xbbbbbbbb -0.00572917
add -1145324613 0xbbbbbbbb -0.00572917
sub -1145324613 0xbbbbbbbb -0.00572917
shr -1145324613 0xbbbbbbbb -0.00572917
asr -1145324613 0xbbbbbbbb -0.00572917
ror -1145324613 0xbbbbbbbb -0.00572917
shl -1145324613 0xbbbbbbbb -0.00572917
min -1145324613 0xbbbbbbbb -0.00572917
max -1145324613 0xbbbbbbbb -0.00572917
and -1145324613 0xbbbbbbbb -0.00572917
or -1145324613 0xbbbbbbbb -0.00572917
xor -1145324613 0xbbbbbbbb -0.00572917
not -1145324613 0xbbbbbbbb -0.00572917
clz -1145324613 0xbbbbbbbb -0.00572917
fmul -1145324613 0xbbbbbbbb -0.00572917
mul24 -1145324613 0xbbbbbbbb -0.00572917
v8muld -1145324613 0xbbbbbbbb -0.00572917
v8min -1145324613 0xbbbbbbbb -0.00572917
v8max -1145324613 0xbbbbbbbb -0.00572917
v8adds -1145324613 0xbbbbbbbb -0.00572917
v8subs -1145324613 0xbbbbbbbb -0.00572917
A0 -1145324613 0xbbbbbbbb -0.00572917
A9 -1145324613 0xbbbbbbbb -0.00572917
A10 -1145324613 0xbbbbbbbb -0.00572917
A11 -1145324613 0xbbbbbbbb -0.00572917
A25 -1145324613 0xbbbbbbbb -0.00572917
A26 -1145324613 0xbbbbbbbb -0.00572917
A27 -1145324613 0xbbbbbbbb -0.00572917
A28 -1145324613 0xbbbbbbbb -0.00572917
A29 -1145324613 0xbbbbbbbb -0.00572917
M0 -1145324613 0xbbbbbbbb -0.00572917
A -16 0xfffffff0 -nan
B -16 0xfffffff0 -nan
fadd -1145324613 0xbbbbbbbb -0.00572917
fsub -1145324613 0xbbbbbbbb -0.00572917
fmin -1145324613 0xbbbbbbbb -0.00572917
fmax -1145324613 0xbbbbbbbb -0.00572917
fminabs -1145324613 0xbbbbbbbb -0.00572917
fmaxabs -1145324613 0xbbbbbbbb -0.00572917
ftoi -1145324613 0xbbbbbbbb -0.00572917
itof -1145324613 0xbbbbbbbb -0.00572917
add -1145324613 0xbbbbbbbb -0.00572917
sub -1145324613 0xbbbbbbbb -0.00572917
shr -1145324613 0xbbbbbbbb -0.00572917
asr -1145324613 0xbbbbbbbb -0.00572917
ror -1145324613 0xbbbbbbbb -0.00572917
shl -1145324613 0xbbbbbbbb -0.00572917
min -1145324613 0xbbbbbbbb -0.00572917
max -1145324613 0xbbbbbbbb -0.00572917
and -1145324613 0xbbbbbbbb -0.00572917
or -1145324613 0xbbbbbbbb -0.00572917
xor -1145324613 0xbbbbbbbb -0.00572917
not -1145324613 0xbbbbbbbb -0.00572917
clz -1145324613 0xbbbbbbbb -0.00572917
fmul -1145324613 0xbbbbbbbb -0.00572917
mul24 -1145324613 0xbbbbbbbb -0.00572917
v8muld -1145324613 0xbbbbbbbb -0.00572917
v8min -1145324613 0xbbbbbbbb -0.00572917
v8max -1145324613 0xbbbbbbbb -0.00572917
v8adds -1145324613 0xbbbbbbbb -0.00572917
v8subs -1145324613 0xbbbbbbbb -0.00572917
A0 -1145324613 0xbbbbbbbb -0.00572917
A9 -1145324613 0xbbbbbbbb -0.00572917
A10 -1145324613 0xbbbbbbbb -0.00572917
A11 -1145324613 0xbbbbbbbb -0.00572917
A25 -1145324613 0xbbbbbbbb -0.00572917
A26 -1145324613 0xbbbbbbbb -0.00572917
A27 -1145324613 0xbbbbbbbb -0.00572917
A28 -1145324613 0xbbbbbbbb -0.00572917
A29 -1145324613 0xbbbbbbbb -0.00572917
M0 -1145324613 0xbbbbbbbb -0.00572917
A -15 0xfffffff1 -nan
B -15 0xfffffff1 -nan
fadd -1145324613 0xbbbbbbbb -0.00572917
fsub -1145324613 0xbbbbbbbb -0.00572917
fmin -1145324613 0xbbbbbbbb -0.00572917
fmax -1145324613 0xbbbbbbbb -0.00572917
fminabs -1145324613 0xbbbbbbbb -0.00572917
fmaxabs -1145324613 0xbbbbbbbb -0.00572917
ftoi -1145324613 0xbbbbbbbb -0.00572917
itof -1145324613 0xbbbbbbbb -0.00572917
add -1145324613 0xbbbbbbbb -0.00572917
sub -1145324613 0xbbbbbbbb -0.00572917
shr -1145324613 0xbbbbbbbb -0.00572917
asr -1145324613 0xbbbbbbbb -0.00572917
ror -1145324613 0xbbbbbbbb -0.00572917
shl -1145324613 0xbbbbbbbb -0.00572917
min -1145324613 0xbbbbbbbb -0.00572917
max -1145324613 0xbbbbbbbb -0.00572917
and -1145324613 0xbbbbbbbb -0.00572917
or -1145324613 0xbbbbbbbb -0.00572917
xor -1145324613 0xbbbbbbbb -0.00572917
not -1145324613 0xbbbbbbbb -0.00572917
clz -1145324613 0xbbbbbbbb -0.00572917
fmul -1145324613 0xbbbbbbbb -0.00572917
mul24 -1145324613 0xbbbbbbbb -0.00572917
v8muld -1145324613 0xbbbbbbbb -0.00572917
v8min -1145324613 0xbbbbbbbb -0.00572917
v8max -1145324613 0xbbbbbbbb -0.00572917
v8adds -1145324613 0xbbbbbbbb -0.00572917
v8subs -1145324613 0xbbbbbbbb -0.00572917
A0 -1145324613 0xbbbbbbbb -0.00572917
A9 -1145324613 0xbbbbbbbb -0.00572917
A10 -1145324613 0xbbbbbbbb -0.00572917
A11 -1145324613 0xbbbbbbbb -0.00572917
A25 -1145324613 0xbbbbbbbb -0.00572917
A26 -1145324613 0xbbbbbbbb -0.00572917
A27 -1145324613 0xbbbbbbbb -0.00572917
A28 -1145324613 0xbbbbbbbb -0.00572917
A29 -1145324613 0xbbbbbbbb -0.00572917
M0 -1145324613 0xbbbbbbbb -0.00572917
A -14 0xfffffff2 -nan
B -14 0xfffffff2 -nan
[...] Now, third value of A,B lines is always -nan.
utils.cpp:82:63: error: use of undeclared identifier 'errno' on macOS
On macOS the build of V0.2.3 fails with the following error:
==> make -C src
mkdir ../obj
g++ -Wall -std=c++11 -g -c -fPIC -o ../obj/utils.o utils.cpp
utils.cpp:82:63: error: use of undeclared identifier 'errno'
throw stringf("Failed to read line from file: %s", strerror(errno));
^
1 error generated.
make: *** [../obj/utils.o] Error 1
This is a successful fix:
inreplace "src/utils.cpp", "#include <unistd.h>",
"#include <unistd.h>\n#include <errno.h>"
mov -, mutex_aqc; compiles to .never
So I had a problem with synchronized VPM access for a while, and it turns out the assembler reduces the following instruction into something - for me - unexpected:
mov -, mutex_acq; or read mutex_acq; (with accompanying instruction)
Expected action: aquire the mutex (read from mutex_acq)
Actually generated code:
or.never nop, mutex_acq, nop;
Expected code that does acquire the mutex:
or nop, mutex_acq, nop;
Workaround (setf is required for it to not automatically set .never flag):
or.setf nop, mutex_acq, nop;
I presume for other signaling reads the .never signal is correct and a valid optimisation to save ALU power, but for the mutex it does not seem work.
Strange mov instruction error
When compile this code:
mov r0, 0x02020202
The result will be:
0x01010101, 0xe00049e0
Disassembled:
ldi r0, 0x1010101
The strange thing is, this behaviour is only for power of 2s and only if bytes repeated 4 times in an integer:
0x02020202, 0x04040404, 0x08080808 ...
Workaround is using ldi instead mov, but I found using mov is much more intuitive.
Documentation of vc4.qinc on VDW is incorrect
Followed the documentation and used vdr_h32/vdr_v32 for DMA store, assuming that VDW and VDR used the same format. I kind of got it to work, but never seemed to fully understand it as there were weird behaviours (vdr_h32 with (1,0,0) for example works fine for writing 16x16 blocks, but has weird behaviour on 16x8 and others).
In short, the documentation should instead point to dma_h32/dma_v32, which are using the correct format. Also, they might be better named as vdw_h32/vdw_v32.
It is still not quite behaving as expected, although that is more likely to be my fault.
Website has invalid HTTPS certificate
This has been the case for a couple months now as far as I am aware, which is sad to see since it has a bunch of good documentation.
Luckily it is still on the wayback machine.
Do you have any plans on bringing it back?
I'm in the process of releasing a thesis and the implementation uses vc4asm (seriously, thank you) and so I would like to cite it, the website or the github repo, doesn't matter.
Nested rep->if->rep causes if to be unterminated
Another minor issue with the preprocessor, the following code will result in the error
Warning P145.20: .if at line 2 in current file unterminated.
.rep x, 2
.if 1
.rep y, 2
nop;
.endr
.endif
.endr
If you remove any of the nests, it works fine again.
Compiling on Ubuntu
I tried to compile 0.2.2 on x64 PC
g++ (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609 and got two errors.
First
AssembleInst.cpp:45:41: error: ‘::isinf’ has not been declared if (fabs(value.fValue) > FLT_MAX && !(::isinf(value.fValue))) ^ AssembleInst.cpp:45:41: note: suggested alternative: In file included from /usr/include/c++/5/random:38:0, from /usr/include/c++/5/bits/stl_algo.h:66, from /usr/include/c++/5/algorithm:62, from AssembleInst.cpp:17: /usr/include/c++/5/cmath:621:5: note: ‘std::isinf’ isinf(_Tp __x)
I took the tip and changed to std::isinf
Second
AssembleInst.cpp:397:12: warning: logical not is only applied to the left hand side of comparison [-Wlogical-not-parentheses] if (!pm2 == pm)
I changed to if ( pm2 != pm ) but on reflection I think you wrote what you intended, how to avoid the messy warning though perhaps if ( (!pm2)==pm )
This is great work !
regards
Andy
Unary operators ceil() and floor() don't take floating point operands
Hello maazl,
It seems there is a bug with ceil and floor that makes it impossible to convert float constants to integers. See the following example, where we try to multiply a value by a power of 2 that normally doesn't fit in the small immediate field.
example.qasm:
.set vec_size, 16
shl r0, elem_num, floor(log2(vec_size))
yields:
example.qasm (2,39): ERROR E10.1: Cannot apply unary operator ceil to operand of type floating point.
FATAL a250: Aborted because of earlier errors.
This bug makes it difficult to use bit shifts in place of multiplication (or worse, division) in situations where numbers need to be manipulated by powers of 2.
Kind regards,
Loek
Problems with nested repetitions
In a nested repetition, e.g.:
.rep a, 2
.rep b, 2
add r0, r0, a*4+b*5
.endr
.endr
The iterator variable of the parent repitition (here: a) will be undefined on compilation and cause an error in the add instruction.
Documentation typo
Hello,
the register table in expressions.html contain vw_busy two times.
Second entry, in line 280, should be vw_wait.
Regards YggdrasiI
P.S. The documentation, bottom at page 55 , says about VPM writes "Up to two writes are queued in a FIFO and writes will stall the QPU when the FIFO is full."
Would this inplicate that a dma store command needs to wait until the VPM write command finished? I did not found any comment (or something like 'vpm_wait') about that.
vcio2-0.1 fails to build on 4.14.89-v7+
sudo make
cat /var/lib/dkms/vcio2/0.1/build/make.logDKMS make.log for vcio2-0.1 for kernel 4.14.89-v7+ (armv7l)
Mon Dec 31 13:06:04 CET 2018
make[1]: Entering directory '/var/lib/dkms/vcio2/0.1/build/src'
make -C /lib/modules/4.14.89-v7+/build M=/var/lib/dkms/vcio2/0.1/build
make[2]: Entering directory '/var/lib/dkms/vcio2/0.1/build/src'
make[2]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule.
AR /var/lib/dkms/vcio2/0.1/build/built-in.o
CC [M] /var/lib/dkms/vcio2/0.1/build/src/vcio2.o
/var/lib/dkms/vcio2/0.1/build/src/vcio2.c:42:24: fatal error: mach/vcio2.h: No such file or directory
#include <mach/vcio2.h>
^
compilation terminated.
scripts/Makefile.build:332: recipe for target '/var/lib/dkms/vcio2/0.1/build/src/vcio2.o' failed
make[3]: *** [/var/lib/dkms/vcio2/0.1/build/src/vcio2.o] Error 1
Makefile:1532: recipe for target '_module_/var/lib/dkms/vcio2/0.1/build' failed
make[2]: *** [_module_/var/lib/dkms/vcio2/0.1/build] Error 2
make[2]: Leaving directory '/home/pi/linux-af369f47021f11e78017c0a98e55cb934b501c36'
Makefile:5: recipe for target 'all' failed
make[1]: *** [all] Error 2
make[1]: Leaving directory '/var/lib/dkms/vcio2/0.1/build/src'mov with packing breaks with 0
Using mov together with packing signals breaks previously packed operations when a 0 is written.
For example:
mov ra10.8asi, 255;
mov ra10.8bsi, 0;
It doesn't matter what you write as the first value, it will always read 0 as well. Any nop; in between seem to have no effect either.
It affects the ALL previous packing operation on that pixel, not just the previous.
If you switch both statements, it works as expected, but that only is an option if you know the values beforehand (e.g. no macros).
If you replace mov with ldi, it works as expected, but without possible optimization as ALU instruction.
If you replace 0 with 1, it also works as expected, or add 1 to each macro, that works as well.
The following works, too, but only for small immediates:
mov ra10, 0;
add ra10.8asi, ra10.8asi, 15;
add ra10.8bsi, ra10.8bsi, 0;
So it's not critical, depending on what you want there are lots of workarounds.
If you need a test set up (printing to framebuffer to visualize) I can provide that.
What I assume the error is: If the compiler sees a mov with any 0 input, it will immediately optimize the packing operation away and write 0 to the whole pixel.
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