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JESD204B core for Migen/MiSoC

Python 100.00%

jesd204b's Introduction

             Copyright 2016-2020 / M-Labs Ltd
             Copyright 2016-2017 / EnjoyDigital

    A small footprint and configurable JESD204B core

[> Features
-----------
PHY:
 - PRBS7/PRBS15/PRBS31 to check link integrity.
 - 8B/10B encoding
 - 32 bits interface
 - Kintex7 support (CPLL up to 5Gbps, QPLL for higher linerates)
 - Kintex Ultrascale support (CPLL up to 6.25Gbps, QPLL for higher linerates)
Core:
 Link:
  - Scrambling to reduce EMI
  - Special characters insertion
  - CGS/ILAS
 Transport:
  - converters <--> lanes mapping

[> Possible improvements
------------------------
- add support for RX (ADC)
- add support for non scrambled mode
- add support for Altera PHYs
- add support for Lattice PHYs
- add support for others Xilinx transceivers

[> Tests
--------
Unit tests are available in ./test/.
To run all the unit tests:
  setup.py test
Tests can also be run individually:
  python3 -m unittest test.test_name

jesd204b's People

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lavender1120 mastadle cutelolly chengzhangxinli harrymakes dbc-chenf minefujiko drewrisinger ngupta-github mfkiwl shanyinshuiyue

jesd204b's Issues

[subclass 1] sample sysref, LMFC, align ILAS to sysref

Figure out if multiple initialization attempts at startup is the expected behaviour

We need multiple initialization attempts to get the link working correctly. We need to:

get statistics on number of initialization attempts.
figure out if this is the case with others cores?
figure out if re-synchronization requests are expected at startup with ADI devices?

Fix transceiver initialization for high linerates

Xxphaligndone does not seem to be asserted for high linerates. Need to understand what is going on...

If there is really a need for splitting between "physical" and "transport" sets of parameters, then the retrieval of parameters should not be done by bruteforcing into each set of parameters, and ignoring errors by silently setting fields that aren't found anywhere to 0.

use elastic buffers instead of async FIFO

enjoy-digital/litejesd204b@2011a5f#commitcomment-19089435

try replacing phy*_tx BUFGs with BUFH/R/MR

License?

We're potentially interested in adding support for the Ultrascale GTH transceivers for use in a superconducting qubit control system but we can't work with a GPL license

Handle the JSYNC pin completely

ditch the elastic buffers

The procedure "Using TX Buffer Bypass in Multi-Lane Manual Mode" in the GTX user guide should make them unnecessary.

Nix build includes test directory in $out

FYI, the Nix build of this package includes the test directory in the $out path. This can cause conflicts with other packages. This should be resolved by the pythonRemoveTestsDirHook in nixpkgs/release-20.03 (see https://github.com/NixOS/nixpkgs/blob/master/pkgs/development/interpreters/python/hooks/python-remove-tests-dir-hook.sh), more just an FYI for your derivation.

always react to SYNC requests

redo link.start so that the core/the link re-enter CGS/ILAS when synchronization is lost (not just the first time after enable)

transceiver initialization/CGS at 10 GHz

For me, with either Xxdlysreset high or skipping phase align, the initialization is about 50% reliable. It either fails to do CGS or SYNC is low.
@enjoy-digital ist this reliable for you?