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lsoracle's Issues

Aborted (Core dumped)

Screenshot from 2022-05-02 16-25-04

Hi, I am facing following issue after using optimization -s 1.
Can someone help me out?
Thanks

Regarding output ports mapping to BLIF/verilog

Hi ,

In the dot file generated , the outputs are named as po*. But in the verilog/blif files as input , the names are of course different for both inputs and outputs.

How to know the mapping of input/output for input blif/verilog to the dot file ?

108 -> po3 [style=solid]
111 -> po4 [style=solid]
120 -> po5 [style=dashed]
122 -> po6 [style=solid]
127 -> po7 [style=solid]
{rank = same; po0; po1; po2; po3; po4; po5; po6; po7; }

Thanks !

Segmentation Fault (Core dumped)

I am trying to read this blif file on LSoracle using read_blif -m filename.blif but its giving me error Segmentation Fault (Core dumped). Is it with size of LUTs ? If I use smaller size LUT then no error. Please suggest some appropriate way.

Following is the code of BLIF file

#--------------------------------------------------------------------------------------#

Generated by Yosys 0.18+10 (git sha1 c98b0e94e, gcc 9.4.0 -fPIC -Os)

.model m4
.inputs v0 v1 v2 v3 v4 v5 v6 v7
.outputs v8.0 v8.1 v8.2 v8.3 v8.4 v8.5 v8.6 v8.7 v8.8 v8.9 v8.10 v8.11 v8.12 v8.13 v8.14 v8.15
.names $false
.names $true
1
.names $undef
.names v0 v2 v3 v1 v6 v7 $abc$7624$new_new_n25__
001111 1
010000 1
010001 1
010100 1
010101 1
010110 1
010111 1
011000 1
011001 1
011010 1
011011 1
011100 1
011101 1
011110 1
011111 1
.names v3 v1 v0 v2 v7 v6 $abc$7624$new_new_n26__
000100 1
000101 1
000110 1
000111 1
001000 1
001001 1
001010 1
001011 1
001100 1
001101 1
001110 1
001111 1
010000 1
010001 1
010010 1
010011 1
011000 1
011001 1
011010 1
011011 1
011100 1
011101 1
011110 1
011111 1
100000 1
100001 1
100010 1
101000 1
101001 1
101010 1
101011 1
101100 1
101101 1
101110 1
101111 1
110101 1
110110 1
110111 1
111000 1
111001 1
111010 1
111011 1
111100 1
111101 1
111110 1
111111 1
.names v3 v4 v1 v6 v2 v7 $abc$7624$new_new_n27__
000001 1
000010 1
000011 1
000100 1
000101 1
000110 1
000111 1
001010 1
001011 1
001100 1
001101 1
001110 1
001111 1
011000 1
011001 1
011010 1
011011 1
011100 1
011101 1
011110 1
011111 1
100000 1
101000 1
101001 1
101010 1
101011 1
101100 1
101101 1
101110 1
101111 1
110000 1
110001 1
110100 1
110101 1
111000 1
111001 1
111010 1
111011 1
111100 1
111101 1
111110 1
111111 1
.names v0 v2 v3 v1 v6 v7 $abc$7624$new_new_n28__
000001 1
000010 1
000011 1
000100 1
000101 1
000110 1
000111 1
010000 1
010001 1
011010 1
011011 1
011100 1
011101 1
011110 1
011111 1
100000 1
100001 1
100010 1
100011 1
100100 1
100101 1
100110 1
100111 1
101000 1
101001 1
101010 1
101011 1
101100 1
101101 1
101110 1
101111 1
110000 1
110001 1
110010 1
110011 1
110100 1
110101 1
110110 1
110111 1
111000 1
111001 1
111010 1
111011 1
.names v4 v5 $abc$7624$new_new_n26__ $abc$7624$new_new_n25__ $abc$7624$new_new_n28__ $abc$7624$new_new_n27__ v8.5
000000 1
000001 1
000010 1
000011 1
001000 1
001001 1
001010 1
001011 1
011000 1
011001 1
011010 1
011011 1
011100 1
011101 1
011110 1
011111 1
100111 1
101000 1
101010 1
101011 1
101110 1
101111 1
110010 1
110011 1
110110 1
110111 1
111010 1
111011 1
111110 1
111111 1
.names v4 v3 v1 v2 v0 v8.0
00000 1
00001 1
00010 1
00011 1
00100 1
00101 1
00110 1
00111 1
01000 1
01001 1
01010 1
01011 1
01100 1
01101 1
01110 1
01111 1
10000 1
10001 1
10010 1
10011 1
10100 1
10101 1
10110 1
10111 1
11000 1
11001 1
11010 1
11011 1
11100 1
11101 1
11110 1
.names v5 v4 v3 v1 v2 v0 v8.8
000000 1
.
Skip code
.
.end

fulladder carryout MIG optimization

hi ,
My blif file is simple containing the logic for carryout for fulladder :

##########################################
#1-bit adder
#Data bits: 1

.model ADDER
.inputs a b cin
.outputs cout

#.names a b k
#10 1
#1 1

#.names k cin o
#10 1
#1 1

.names a b cin cout
11- 1
1-1 1
-11 1

.end

##########################################

My steps in lsoracle are :

lsoracle> read fa.blif
AIG network stored
lsoracle> oracle --mig
fa partitioned 1 times
0 AIGs and 1 MIGs
No change made to network
MIG network stored
lsoracle> ps -m
nodes: 12
inputs: 3
latches: 0
outputs: 1
MAJ nodes: 8
MIG level: 4
lsoracle [mig]> optimization --mig
0 AIGs and 1 MIGs
Final ntk size = 4 and depth = 3
Final number of latches = 0
Area Delay Product = 12
Full Optimization: 17ms
Finished optimization
lsoracle [mig]> write_dot -m --filename fa.dot
lsoracle [mig]> write_verilog -m --filename carry.v

The verilog out looks like :

module top(a , b , cin , cout );
input a , b , cin ;
output cout ;
wire new_n4, new_n5, new_n6, new_n7;
assign new_n4 = ( a & b ) | ( a & cin ) | ( b & cin );
assign new_n5 = a & cin ;
assign new_n6 = b & ~new_n5 ;
assign new_n7 = ( ~b & new_n4 ) | ( ~b & new_n6 ) | ( new_n4 & new_n6 );
assign cout = new_n7 ;
endmodule

But the expectation is that the cout will be only = ( a & b ) | ( a & cin ) | ( b & cin );
So MIG will be only the majority function of a,b,cin.

Are there extra steps involved to get this optimized ?

Thanks!

error: ‘write_child’ is not a member of ‘oracle’

An error when make

[ 94%] Building CXX object core/CMakeFiles/unit_tests.dir/kahypar_config.cpp.o
[ 94%] Building CXX object core/CMakeFiles/unit_tests.dir/kahypar_temp_config.cpp.o
[ 94%] Building CXX object core/CMakeFiles/unit_tests.dir/algorithms/optimization/resynthesis.cpp.o
[ 96%] Building CXX object core/CMakeFiles/unit_tests.dir/utility.cpp.o
[ 96%] Building CXX object core/CMakeFiles/unit_tests.dir/algorithms/partitioning/__tests__/sap_test.cpp.o
[ 96%] Building CXX object core/CMakeFiles/unit_tests.dir/algorithms/partitioning/__tests__/partition_manager_junior_test.cpp.o
[ 96%] Building CXX object core/CMakeFiles/lsoracle.dir/lsoracle.cpp.o
[ 98%] Building CXX object core/CMakeFiles/lsoracle.dir/algorithms/optimization/resynthesis.cpp.o
[ 98%] Building CXX object core/CMakeFiles/lsoracle.dir/kahypar_temp_config.cpp.o
[ 98%] Building CXX object core/CMakeFiles/lsoracle.dir/kahypar_config.cpp.o
[ 98%] Building CXX object core/CMakeFiles/lsoracle.dir/utility.cpp.o
In file included from /lustre/S/matianyun/LSOracle/core/lsoracle.cpp:106:0:
/lustre/S/matianyun/LSOracle/core/commands/output/write_partition.hpp: In member function ‘void alice::write_partition_command::write_part(std::__cxx11::string)’:
/lustre/S/matianyun/LSOracle/core/commands/output/write_partition.hpp:75:21: error: ‘write_child’ is not a member of ‘oracle’
             oracle::write_child<network>(i, partitions, verilog);
                     ^~~~~~~~~~~
/lustre/S/matianyun/LSOracle/core/commands/output/write_partition.hpp:75:40: error: expected primary-expression before ‘>’ token
             oracle::write_child<network>(i, partitions, verilog);
                                        ^
At global scope:
cc1plus: warning: unrecognized command line option ‘-Wno-unneeded-internal-declaration’
make[2]: *** [core/CMakeFiles/lsoracle.dir/lsoracle.cpp.o] Error 1
make[2]: *** Waiting for unfinished jobs....
[ 98%] Linking CXX executable unit_tests
[ 98%] Built target unit_tests
make[1]: *** [core/CMakeFiles/lsoracle.dir/all] Error 2
make: *** [all] Error 2

README fixes needed

README refers to cmake 3.9 being required, but it looks like kahypar requires 3.12

building issue of filesystem header

Hi. I'm trying to rebuild the newest version of LSOracle, and stuck in an error from . The log shows below:
In file included from /home/jingxiao/Tools/LSOracle/core/lsoracle.cpp:56:0: /home/jingxiao/Tools/LSOracle/core/commands/output/get_all_partitions.hpp:17:10: fatal error: filesystem: No such file or directory #include <filesystem> ^~~~~~~~~~~~ compilation terminated. core/CMakeFiles/lsoracle.dir/build.make:62: recipe for target 'core/CMakeFiles/lsoracle.dir/lsoracle.cpp.o' failed make[2]: *** [core/CMakeFiles/lsoracle.dir/lsoracle.cpp.o] Error 1 CMakeFiles/Makefile2:1217: recipe for target 'core/CMakeFiles/lsoracle.dir/all' failed make[1]: *** [core/CMakeFiles/lsoracle.dir/all] Error 2 Makefile:129: recipe for target 'all' failed make: *** [all] Error 2

Could you please have a look? Thank you.

performance question

Hi!
I have tested the circuit, as well as EPFL combinational circuits, you mentioned in your paper and LSOracle2.0 with LSOracle and abc resyn2rs script, but the result shows that abc resyn2rs script performs better in most cases.
I'm wondering there may be some mistakes in my test flow which leads to the problem above.
May you guys give a detailed guide on how to do a correct test?
Thanks inadvance sincerely!

Interactive sessions exit on command parse errors instead of continue

Right now any error calls system exit. I would prefer that during an interactive session, recoverable errors like command parse don't kill the process and allow me to correct the command.
Change exit calls to throw exceptions, then depending on interactive/non-interactive either kill the process or just show user an error

Program execution stuck during karypar

I was using the oracle command,and then the problem occured .

image

Then I debugged the code ,finding that it had executed "HEAVY_PREPROCESSING_ASSERT" in "modularity.h:121' .And that should not happen ,because the variable enable_heavy_assert is false.

image

20230522181605

image

How can I fix this?

Exporting a top-module in Verilog containing the instantiations of the sub-circuits

I partitioned a small circuit (a 2-bit Ripple-Carry Adder named "adder_2") into two subcircuits, and two subcircuits appeared with the names "adder_2_0.v" and "adder_2_1.v".
I wondered if there is a way to export a merged top-level module in Verilog format in which the two subcircuits are instantiated.
More precisely, what I'm looking for is the following:

#===================================================
module top_adder_2_merged_after_partitioning(inputs, outputs);

inputs...
outputs...
wires...

adder_2_0 U0(inputs|wires, outputs|wires)
adder_2_1 U1(inputs|wires, outputs|wires)
#===================================================

If there is no such command, is there a way (maybe through other commands such as "partition_detail") to export the information on how to connect the two subcircuits to create the desired top-level module?

Regarding generation of MIG views

Hi ,

I am trying to generate a MIG network after optimization in readable format ( verilog , other texts etc)
What is the correct command to dump that after reading blif/aig format ?

For example for cout = xy + yz + zx, MIG network could be in format like below :

Y1 = MAJORITY (z , x_bar , y);
Y2 = MAJORITY (y_bar , x_bar , z_bar)
COUT = MAJORITY(x , Y1 , Y2);

Thanks !

Update documentation with kahypar config file information

Hello ,

I am trying to load below example file and run oracle on it. But the shell crashes. With the message "Could not load context file at: /usr/local/share/lsoracle/test.ini"

lsoracle> read lib/mockturtle/test/benchmarks/c3540.aig
AIG network stored
lsoracle> oracle
Could not load context file at: /usr/local/share/lsoracle/test.ini

Can you please help regarding the same ?

OR gate not able to map to MIG

Hello ,

I wrote a simple OR gate verilog and Yosys blif outputs the following which seems ok


Generated by Yosys 0.9+4081 (git sha1 1667ad65, gcc 9.3.0-17ubuntu1~20.04 -fPIC -Os)

.model top
.inputs c d
.outputs q
.names $false
.names $true
1
.names $undef
.names c d q
1- 1
-1 1
.end

Now if i follow below steps :

read_blif Yosys/or.blif -a
ps -m
write_verilog -m --filename or_oracel.v

The verilog file written above looks like below (an XOR gate..):

module top(c , d , q );
input c , d ;
output q ;
wire new_n3, new_n4, new_n5;
assign new_n3 = ~c & d ;
assign new_n4 = c & ~d ;
assign new_n5 = new_n3 | new_n4 ;
assign q = new_n5 ;
endmodule

Is there any issue in steps Or there is some issue in the code ??

Thanks

Problem about command "oracle"

Hi
I'm having a problem with the LSOracle.

This is my step:
lsoracle> read_aig 0.aig
lsoracle> oracle
lsoracle> write_blif -m 0.blif

But I am using the "cec" of the tool "ABC", and the verificationis not equivalent.

abc 01> cec 0.aig 0.blif
Networks are NOT EQUIVALENT. Time = 0.00 sec
Verification failed for at least 8 outputs: output_47 output_50 output_53 ...
Output output_47: Value in Network1 = 0. Value in Network2 = 1.
Input pattern: input_45=0 input_46=0 input_44=0

I have tried other cases, and this situation will also occur.
Upload a case below.
Thanks!
0.zip

Error in `lsoracle': free(): invalid pointer: 0x00000000344e8f00

Hi
I'm having a problem with the LSOracle.

This is my step:
lsoracle> read_aig abc_bef.aig
lsoracle> oracle --strategy depth

But crash in aig_scripts3.

***** Error in `lsoracle': free(): invalid pointer: 0x00000000344e8f00 ***
======= Backtrace: =========
/usr/lib64/libc.so.6(+0x766c0)[0x7f3da0adc6c0]
/usr/lib64/libc.so.6(+0x7c1d8)[0x7f3da0ae21d8]
/usr/lib64/libc.so.6(+0x7cdbc)[0x7f3da0ae2dbc]
lsoracle[0x532738]
lsoracle[0x53289a]
lsoracle[0x4830ba]
lsoracle[0x6770c5]**

image
Is this because the cache exploded?
I'm locating the problem in function mockturtle::refactoring(aig, rf_resyn, rp);.
But I don't know how to solve it.
The zip contains the AIG circuit I tested.

Upload a case below.
Thanks!

abc_bef.zip

compiler warning

When we compile lsoracle in OpenRoad I see in the logs:

15:45:32  CMakeFiles/lsoracle.dir/lsoracle.cpp.o: In function `int alice::show_command<std::shared_ptr<mockturtle::names_view<mockturtle::aig_network> >, std::shared_ptr<oracle::partition_manager<mockturtle::names_view<mockturtle::aig_network> > >, std::shared_ptr<mockturtle::names_view<mockturtle::mig_network> >, std::shared_ptr<oracle::partition_manager<mockturtle::names_view<mockturtle::mig_network> > >, std::shared_ptr<mockturtle::names_view<mockturtle::xag_network> >, std::shared_ptr<mockturtle::names_view<mockturtle::klut_network> > >::show_store<std::shared_ptr<mockturtle::names_view<mockturtle::klut_network> > >()':
15:45:32  lsoracle.cpp:(.text._ZN5alice12show_commandIJSt10shared_ptrIN10mockturtle10names_viewINS2_11aig_networkEEEES1_IN6oracle17partition_managerIS5_EEES1_INS3_INS2_11mig_networkEEEES1_INS8_ISC_EEES1_INS3_INS2_11xag_networkEEEES1_INS3_INS2_12klut_networkEEEEEE10show_storeISL_EEiv[_ZN5alice12show_commandIJSt10shared_ptrIN10mockturtle10names_viewINS2_11aig_networkEEEES1_IN6oracle17partition_managerIS5_EEES1_INS3_INS2_11mig_networkEEEES1_INS8_ISC_EEES1_INS3_INS2_11xag_networkEEEES1_INS3_INS2_12klut_networkEEEEEE10show_storeISL_EEiv]+0x2ab): warning: the use of `tmpnam' is dangerous, better use `mkstemp'

Please clean this up when you get a chance. Thanks.

Read bllif error

Hi ,

My blif file contains the below lines :

.model TopLevel432b
.inputs E[0] E[1] E[2] E[3] E[4] E[5] E[6] E[7] E[8] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] B[8] C[0] C[1] C[2] C[3] C[4] C[5] C[6] C[7] C[8]
.outputs PA PB PC Chan[0] Chan[1] Chan[2] Chan[3]
.names $false
.names $true
1
.names $undef
.subckt PriorityA A[0]=A[0] A[1]=A[1] A[2]=A[2] A[3]=A[3] A[4]=A[4] A[5]=A[5] A[6]=A[6] A[7]=A[7] A[8]=A[8] E[0]=E[0] E[1]=E[1] E[2]=E[2] E[3]=E[3] E[4]=E[4] E[5]=E[5] E[6]=E[6] E[7]=E[7] E[8]=E[8] PA=PA X1[0]=X1[0] X1[1]=X1[1] X1[2]=X1[2] X1[3]=X1[3] X1[4]=X1[4] X1[5]=X1[5] X1[6]=X1[6] X1[7]=X1[7] X1[8]=X1[8]
.subckt PriorityB B[0]=B[0] B[1]=B[1] B[2]=B[2] B[3]=B[3] B[4]=B[4] B[5]=B[5] B[6]=B[6] B[7]=B[7] B[8]=B[8] E[0]=E[0] E[1]=E[1] E[2]=E[2] E[3]=E[3] E[4]=E[4] E[5]=E[5] E[6]=E[6] E[7]=E[7] E[8]=E[8] PB=PB X1[0]=X1[0] X1[1]=X1[1] X1[2]=X1[2] X1[3]=X1[3] X1[4]=X1[4] X1[5]=X1[5] X1[6]=X1[6] X1[7]=X1[7] X1[8]=X1[8] X2[0]=X2[0] X2[1]=X2[1] X2[2]=X2[2] X2[3]=X2[3] X2[4]=X2[4] X2[5]=X2[5] X2[6]=X2[6] X2[7]=X2[7] X2[8]=X2[8]
.subckt PriorityC C[0]=C[0] C[1]=C[1] C[2]=C[2] C[3]=C[3] C[4]=C[4] C[5]=C[5] C[6]=C[6] C[7]=C[7] C[8]=C[8] E[0]=E[0] E[1]=E[1] E[2]=E[2] E[3]=E[3] E[4]=E[4] E[5]=E[5] E[6]=E[6] E[7]=E[7] E[8]=E[8] PC=PC X1[0]=X1[0] X1[1]=X1[1] X1[2]=X1[2] X1[3]=X1[3] X1[4]=X1[4] X1[5]=X1[5] X1[6]=X1[6] X1[7]=X1[7] X1[8]=X1[8] X2[0]=X2[0] X2[1]=X2[1] X2[2]=X2[2] X2[3]=X2[3] X2[4]=X2[4] X2[5]=X2[5] X2[6]=X2[6] X2[7]=X2[7] X2[8]=X2[8]
.subckt EncodeChan A[0]=A[0] A[1]=A[1] A[2]=A[2] A[3]=A[3] A[4]=A[4] A[5]=A[5] A[6]=A[6] A[7]=A[7] A[8]=A[8] B[0]=B[0] B[1]=B[1] B[2]=B[2] B[3]=B[3] B[4]=B[4] B[5]=B[5] B[6]=B[6] B[7]=B[7] B[8]=B[8] C[0]=C[0] C[1]=C[1] C[2]=C[2] C[3]=C[3] C[4]=C[4] C[5]=C[5] C[6]=C[6] C[7]=C[7] C[8]=C[8] E[0]=E[0] E[1]=E[1] E[2]=E[2] E[3]=E[3] E[4]=E[4] E[5]=E[5] E[6]=E[6] E[7]=E[7] E[8]=E[8] I[0]=I[0] I[1]=I[1] I[2]=I[2] I[3]=I[3] I[4]=I[4] I[5]=I[5] I[6]=I[6] I[7]=I[7] I[8]=I[8] PA=PA PB=PB PC=PC
.subckt DecodeChan Chan[0]=Chan[0] Chan[1]=Chan[1] Chan[2]=Chan[2] Chan[3]=Chan[3] I[0]=I[0] I[1]=I[1] I[2]=I[2] I[3]=I[3] I[4]=I[4] I[5]=I[5] I[6]=I[6] I[7]=I[7] I[8]=I[8].end

But reading in lsoracle is giving errors as below: Is the .subckt definition for blif supported ?

[e] cannot parse line .subckt TopLevel432b A[0]=in102 A[1]=in89 A[2]=in76 A[3]=in63 A[4]=in50 A[5]=in37 A[6]=in24 A[7]=in11 A[8]=in1 B[0]=in112 B[1]=in99 B[2]=in86 B[3]=in73 B[4]=in60 B[5]=in47 B[6]=in34 B[7]=in21 B[8]=in8 C[0]=in115 C[1]=in105 C[2]=in92 C[3]=in79 C[4]=in66 C[5]=in53 C[6]=in40 C[7]=in27 C[8]=in14 Chan[0]=Chan[0] Chan[1]=Chan[1] Chan[2]=Chan[2] Chan[3]=Chan[3] E[0]=in108 E[1]=in95 E[2]=in82 E[3]=in69 E[4]=in56 E[5]=in43 E[6]=in30 E[7]=in17 E[8]=in4 PA=PA PB=PB PC=PC
[e] cannot parse line .subckt PriorityA A[0]=A[0] A[1]=A[1] A[2]=A[2] A[3]=A[3] A[4]=A[4] A[5]=A[5] A[6]=A[6] A[7]=A[7] A[8]=A[8] E[0]=E[0] E[1]=E[1] E[2]=E[2] E[3]=E[3] E[4]=E[4] E[5]=E[5] E[6]=E[6] E[7]=E[7] E[8]=E[8] PA=PA X1[0]=X1[0] X1[1]=X1[1] X1[2]=X1[2] X1[3]=X1[3] X1[4]=X1[4] X1[5]=X1[5] X1[6]=X1[6] X1[7]=X1[7] X1[8]=X1[8]
[e] cannot parse line .subckt PriorityB B[0]=B[0] B[1]=B[1] B[2]=B[2] B[3]=B[3] B[4]=B[4] B[5]=B[5] B[6]=B[6] B[7]=B[7] B[8]=B[8] E[0]=E[0] E[1]=E[1] E[2]=E[2] E[3]=E[3] E[4]=E[4] E[5]=E[5] E[6]=E[6] E[7]=E[7] E[8]=E[8] PB=PB X1[0]=X1[0] X1[1]=X1[1] X1[2]=X1[2] X1[3]=X1[3] X1[4]=X1[4] X1[5]=X1[5] X1[6]=X1[6] X1[7]=X1[7] X1[8]=X1[8] X2[0]=X2[0] X2[1]=X2[1] X2[2]=X2[2] X2[3]=X2[3] X2[4]=X2[4] X2[5]=X2[5] X2[6]=X2[6] X2[7]=X2[7] X2[8]=X2[8]
[e] cannot parse line .subckt PriorityC C[0]=C[0] C[1]=C[1] C[2]=C[2] C[3]=C[3] C[4]=C[4] C[5]=C[5] C[6]=C[6] C[7]=C[7] C[8]=C[8] E[0]=E[0] E[1]=E[1] E[2]=E[2] E[3]=E[3] E[4]=E[4] E[5]=E[5] E[6]=E[6] E[7]=E[7] E[8]=E[8] PC=PC X1[0]=X1[0] X1[1]=X1[1] X1[2]=X1[2] X1[3]=X1[3] X1[4]=X1[4] X1[5]=X1[5] X1[6]=X1[6] X1[7]=X1[7] X1[8]=X1[8] X2[0]=X2[0] X2[1]=X2[1] X2[2]=X2[2] X2[3]=X2[3] X2[4]=X2[4] X2[5]=X2[5] X2[6]=X2[6] X2[7]=X2[7] X2[8]=X2[8]
[e] cannot parse line .subckt EncodeChan A[0]=A[0] A[1]=A[1] A[2]=A[2] A[3]=A[3] A[4]=A[4] A[5]=A[5] A[6]=A[6] A[7]=A[7] A[8]=A[8] B[0]=B[0] B[1]=B[1] B[2]=B[2] B[3]=B[3] B[4]=B[4] B[5]=B[5] B[6]=B[6] B[7]=B[7] B[8]=B[8] C[0]=C[0] C[1]=C[1] C[2]=C[2] C[3]=C[3] C[4]=C[4] C[5]=C[5] C[6]=C[6] C[7]=C[7] C[8]=C[8] E[0]=E[0] E[1]=E[1] E[2]=E[2] E[3]=E[3] E[4]=E[4] E[5]=E[5] E[6]=E[6] E[7]=E[7] E[8]=E[8] I[0]=I[0] I[1]=I[1] I[2]=I[2] I[3]=I[3] I[4]=I[4] I[5]=I[5] I[6]=I[6] I[7]=I[7] I[8]=I[8] PA=PA PB=PB PC=PC
[e] cannot parse line .subckt DecodeChan Chan[0]=Chan[0] Chan[1]=Chan[1] Chan[2]=Chan[2] Chan[3]=Chan[3] I[0]=I[0] I[1]=I[1] I[2]=I[2] I[3]=I[3] I[4]=I[4] I[5]=I[5] I[6]=I[6] I[7]=I[7] I[8]=I[8]
parsing failed

Thanks !

some questions in structure aware partition method

I used EPFL's test circuit as follows:
image
Discover the structure aware partition method in previous versions,“-s”option.
Many circuits in the figure cannot be partitioned with 'partitioning -s', and a Segmentation fault (core dumped) will appear.
the version i used is #75.

make error

Hi ,

Getting below error while make command :

[ 75%] Built target kahypar
[ 89%] Built target unit_tests
[ 89%] Building CXX object core/CMakeFiles/lsoracle.dir/lsoracle.cpp.o
In file included from /home/ratul619/LSoracle/LSOracle/core/lsoracle.cpp:145:
/home/ratul619/LSoracle/LSOracle/core/commands/optimization/optimize.hpp: In member function ‘void alice::optimize_command::synth(std::string)’:
/home/ratul619/LSoracle/LSOracle/core/commands/optimization/optimize.hpp:76:27: error: ‘optimize_resynthesis’ is not a member of ‘oracle’
76 | ntk_result = oracle::optimize_resynthesismockturtle::aig_network(partitions_jr, abc_exec);
| ^~~~~~~~~~~~~~~~~~~~
/home/ratul619/LSoracle/LSOracle/core/commands/optimization/optimize.hpp:76:71: error: expected primary-expression before ‘>’ token
76 | ntk_result = oracle::optimize_resynthesismockturtle::aig_network(partitions_jr, abc_exec);
| ^
/home/ratul619/LSoracle/LSOracle/core/commands/optimization/optimize.hpp:78:14: error: ‘optimization_strategy’ is not a member of ‘oracle’; did you mean ‘optimization_test’?
78 | oracle::optimization_strategy strategy;
| ^~~~~~~~~~~~~~~~~~~~~
| optimization_test
/home/ratul619/LSoracle/LSOracle/core/commands/optimization/optimize.hpp:80:3: error: ‘strategy’ was not declared in this scope
80 | strategy = oracle::optimization_strategy::depth;
| ^~~~~~~~
/home/ratul619/LSoracle/LSOracle/core/commands/optimization/optimize.hpp:80:22: error: ‘oracle::optimization_strategy’ has not been declared
80 | strategy = oracle::optimization_strategy::depth;
| ^~~~~~~~~~~~~~~~~~~~~
/home/ratul619/LSoracle/LSOracle/core/commands/optimization/optimize.hpp:82:3: error: ‘strategy’ was not declared in this scope
82 | strategy = oracle::optimization_strategy::size;
| ^~~~~~~~
/home/ratul619/LSoracle/LSOracle/core/commands/optimization/optimize.hpp:82:22: error: ‘oracle::optimization_strategy’ has not been declared
82 | strategy = oracle::optimization_strategy::size;
| ^~~~~~~~~~~~~~~~~~~~~
/home/ratul619/LSoracle/LSOracle/core/commands/optimization/optimize.hpp:84:3: error: ‘strategy’ was not declared in this scope
84 | strategy = oracle::optimization_strategy::balanced;
| ^~~~~~~~
/home/ratul619/LSoracle/LSOracle/core/commands/optimization/optimize.hpp:84:22: error: ‘oracle::optimization_strategy’ has not been declared
84 | strategy = oracle::optimization_strategy::balanced;
| ^~~~~~~~~~~~~~~~~~~~~
/home/ratul619/LSoracle/LSOracle/core/commands/optimization/optimize.hpp:87:34: error: ‘optimize_basic’ is not a member of ‘oracle’
87 | ntk_result = oracle::optimize_basic(partitions_jr, abc_exec, strategy);
| ^~~~~~~~~~~~~~
/home/ratul619/LSoracle/LSOracle/core/commands/optimization/optimize.hpp:87:56: error: expected primary-expression before ‘>’ token
87 | ntk_result = oracle::optimize_basic(partitions_jr, abc_exec, strategy);
| ^
/home/ratul619/LSoracle/LSOracle/core/commands/optimization/optimize.hpp:87:83: error: ‘strategy’ was not declared in this scope
87 | ntk_result = oracle::optimize_basic(partitions_jr, abc_exec, strategy);
| ^~~~~~~~

In file included from /home/ratul619/LSoracle/LSOracle/core/lsoracle.cpp:63:
/home/ratul619/LSoracle/LSOracle/core/algorithms/optimization/mab.hpp: In function ‘std::string oracle::abc_stats_commmands(int, int, int)’:
/home/ratul619/LSoracle/LSOracle/core/algorithms/optimization/mab.hpp:380:1: warning: control reaches end of non-void function [-Wreturn-type]
380 | }
| ^
/home/ratul619/LSoracle/LSOracle/core/algorithms/optimization/mab.hpp: In function ‘float oracle::get_results_universe(std::string, int)’:
/home/ratul619/LSoracle/LSOracle/core/algorithms/optimization/mab.hpp:699:1: warning: control reaches end of non-void function [-Wreturn-type]
699 | }
| ^
/home/ratul619/LSoracle/LSOracle/core/algorithms/optimization/mab.hpp: In function ‘std::vector oracle::sample(int, int, int, std::vector<std::__cxx11::basic_string >, std::string, std::string, std::vector<std::vector >&, std::vector<std::vector >&, std::vector<std::__cxx11::basic_string >&, int, int, int, int, std::string)’:
/home/ratul619/LSoracle/LSOracle/core/algorithms/optimization/mab.hpp:1173:15: warning: ignoring return value of ‘int system(const char*)’, declared with attribute warn_unused_result [-Wunused-result]
1173 | system(commands_vec[i].c_str());
| ~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/home/ratul619/LSoracle/LSOracle/core/algorithms/optimization/mab.hpp: In function ‘void oracle::bayes_flow_tune(const char*, int, int, int, int, int, int, int)’:
/home/ratul619/LSoracle/LSOracle/core/algorithms/optimization/mab.hpp:1277:52: warning: ignoring return value of ‘int system(const char*)’, declared with attribute warn_unused_result [-Wunused-result]
1277 | string remove_log = "rm "+design+".log"; system(remove_log.c_str()); //remove log file if exists
| ~~~~~~^~~~~~~~~~~~~~~~~~~~
At global scope:
cc1plus: warning: unrecognized command line option ‘-Wno-unneeded-internal-declaration’
make[2]: *** [core/CMakeFiles/lsoracle.dir/build.make:67: core/CMakeFiles/lsoracle.dir/lsoracle.cpp.o] Error 1
make[1]: *** [CMakeFiles/Makefile2:4282: core/CMakeFiles/lsoracle.dir/all] Error 2

Any ideas ?? I tried to search , but didnt get any concrete solution

Thanks

"get_all_partitions" does not work

It appears some of the commands described in the documentation no longer work. Could you help with what I am trying to do?
I am able to read in the AIG network. I want to partition it into n partitions, and write out all the partitions separately in verilog. What would the best set of commands to this?

./lsoracle: not found

I am facing issues if I use optimize --strategy 1 on a blif file read as AIG network.
WhatsApp Image 2022-05-01 at 7 05 02 PM

Can you please help me out ?
Thanks

Embed kahypar config file in executable

The location of the KaHyPar configuration file is causing no end of confusion to users. It was previously hard coded to '../../core/test.ini' - recent change made the flags on the commands actually allow specifying the location and the default location /usr/local/share/lsoracle/test.ini based off the common install path in unix. This is all very brittle, so by default the configuration should be embedded in the executable and either sent in directly or loaded from a temp file.

MIG optimization

Hi , i generated a blif using yosys for full adder. And when i try to use lsoracle for optimization , doesnt seem to give optimized result. For example , i expect the cout to be just one level - majority between In1 , In2 & Cin.

.model fullAdder
.inputs In1 In2 Cin
.outputs Sum Cout
.names $false
.names $true
1
.names $undef
.names In1 In2 $xor$fa.v:25$1_Y
10 1
01 1
.names $xor$fa.v:25$1_Y Cin Sum
10 1
01 1
.names In1 In2 $and$fa.v:27$3_Y
11 1
.names In2 Cin $and$fa.v:27$4_Y
11 1
.names $and$fa.v:27$3_Y $and$fa.v:27$4_Y $or$fa.v:27$5_Y
1- 1
-1 1
.names Cin In1 $and$fa.v:27$6_Y
11 1
.names $or$fa.v:27$5_Y $and$fa.v:27$6_Y Cout
1- 1
-1 1
.end

Commands used :

read_blif -m fa.blif
migtune
migscript

MIG logic depth 5 nodes 13
MIG logic depth 5 nodes 13
Final ntk size = 13 and depth = 5
Area Delay Product = 65
Full Optimization: 6ms
Finished optimization

Any more optimization step i am missing ?? Thanks

build problems in kahypar

I am having build problems, errors arising in building kayhypar library. When I download kayhypar separately from its own repo, it compiles fine. The error is coming from the folder that is included with LSOracle. I am using macOSX 10.14.4

/Users/sheriefreda/Tools/LSOracle/lib/kahypar/kahypar/partition/refinement/flow/most_balanced_minimum_cut.h:372:10: error: no member named 'random_shuffle' in namespace 'std'
std::random_shuffle(start_nodes.begin(), start_nodes.end());
~~~~~^

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