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View Code? Open in Web Editor NEWExperiment with LiteX on proFPGA systems
License: BSD 2-Clause "Simplified" License
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antmicrolitex-on-profpga-systems's Issues
platforms/profpga_vu19p.py: fix pinouts names on TA1, fill missing ones and add others TA connectors.
Random names have been on on TA1 connectors (since no access to documentation), we should use the real ones, fill all the pins and also define the others connectors. This will allow selecting site of the adapter in the target file.
adapters: add more adapters (ex: DDR4, Ethernet, etc...) and integrate them in initial proFPGA VU19P target.
We are currently only supporting the PCIe adapter, it would be useful to test the infrastructure with DDR4, Ethernet adapters and integrate them with LiteDRAM/LiteEth.
Use proFPGA GUI to discover the adapters to generate a configuration file that could be used to create a target.
The proFPGA GUI could be used to discover the adapter mounted on the system. We could use results from it to generate a configuration file, that we could directly reuse to generate the design.
The user would then plug the adapters, run the GUI or a custom script and would be able to directly build a design for this configuration.
Before loading a bitstream to the the board, we could also use the proFPGA GUI to check the current configuration against the bitstream and make sure we prevent loading bitstream if the configuration has changed (and eventually suggest to rebuild it).
adapters/pcie_gen3_8_lane_kit: use real pins names and add pcie_x1, x2 if useful.
Random names have been on on TA1 connectors (since no access to documentation), we should use the real ones and maybe allow PCIe X1, X2 if useful.
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