Does the de1-soc target supports using the hard processor? about litex-boards HOT 8 CLOSED

If it does not, I would like to contribute and try to add the support for the HPS

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Do you mean for all Cyclone V FPGAs?

From what I understand of the code I should modify the SoCCore or create a new class.

I should modify the add_cpu() method to use the HPS instead of a softcpu.

Should I do that inside the de1soc.py?

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According the the documentation the device only supports AXI-3.

But the conde from litex axi interconnect implements AXI-4 Full/Lite.

Will it be compatible to AXI-3?

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@ilesser: adding support for the HPS could be useful yes (as we are supporting creating SoCs aroudn the Zynq PS). We could had support to AXI-3, the difference with AXI-4 should not be very big and mostly located on the burst capabilities i think. You could look at SoCZynq to find some inspiration.

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@ilesser: adding support for the HPS could be useful yes (as we are supporting creating SoCs aroudn the Zynq PS). We could had support to AXI-3, the difference with AXI-4 should not be very big and mostly located on the burst capabilities i think. You could look at SoCZynq to find some inspiration.

Thanks!
I was reading about axi3 and axi4 and there are only a few extra signals between them.

I have already forked litex and I am working in a soc_cv.py.
I will create an issue there and a pull request.
I want to use axi instead of wishbone and that will take me a while.
I am also going through some qsys projects to try to isolate an IP that can be used for the instantiation.

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The easiest solution is to bridge the AXI to the Wishbone as we are doing on the Zynq. This will be easier to merge and there are also some work planned to support AXI directly in the SoC.

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To avoid too much duplication, let's continue the discussion in enjoy-digital/litex#466.

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