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trabucayre avatar trabucayre commented on August 18, 2024

Hello,
Yes DDR3 is not working and is a WIP.
Sipeed example uses Gowin's DDR3 encrypted IP. But since Gowin doesn't provides real documentation about primitives required to add this support it's more difficult/long to have a working support.
If you need SDRAM it's possible to plug a Mister SDRAM extension into SDRAM dock's connector.

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enjoy-digital avatar enjoy-digital commented on August 18, 2024

@agv100: We've planned some to work on this in the following weeks/months. This will probably happen soon but we are working on others features in priority on other features for now.

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enjoy-digital avatar enjoy-digital commented on August 18, 2024

While continuing this work, it could be worth checking if a specific LOC constraint is required to get the DDR3 working, as it is for the AE350 SOC:

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briansune avatar briansune commented on August 18, 2024

@enjoy-digital
@trabucayre

I would like to give it a try on the modified board.
The background is because before 19.9 is released the DDR3 IP cannot run AE350 with non-Micron DDR.
You can read more on here about what we had done:
https://github.com/briansune/Tang-Mega-138K-AE350-Demo

If such design is based on the default official board hardware then my current hardware is 100% aligned.

Meanwhile from the generated verilog file.
I can see the DDR clock is using a 1:2 rather than 1:4?
GW5AST do not support 1:2 physical timing it will fail surely.

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