Colorlight 5A-75B: Connection Timed out by RemoteClient about litex-boards HOT 5 CLOSED

Hi @r4d10n,

as described in #40, there are still some timing optimization to do. But on next monday i could provide you a bitstream that is working on my hardware to see if you are able to reproduce the results with it.

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@r4d10n: Please find attached a bitstream i just generated and tested on my ColorLight 5A-75B V7.0. Can you verify it also work on your hardware? To test it, connect the Ethernet PHY0 (the one near the power connector) to your network and try to ping 192.168.1.50.

Note that there are large timings violations that need to be fixed as described in my previous answer, but i haven't seen issues while doing the hardware tests. If it's not working, try to be sure to be connected to a 1Gbps port of a switch/host.

colorlight_5a_75b_v7.0_2020_02_24_etherbone_phy0.zip

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Thanks @r4d10n for the feedback. The issue you see are expected since the script was only reading data from the UART. If you want to be able to interact with the BIOS, you can use wishbone-tool. I just added instructions to use it: 4a84e9b.

For work to support 32-bit datawidth is related to the work in progress to support 10Gbps: enjoy-digital/liteeth#21 I'm planing to spend some time soon on that so that we can finish and merge the work, that's maybe a bit complicated to start with. If you're familar with FPGA development and would like to work on that i could try to give you directions.

Otherwise, for Linux, the minimum we are currently supporting is 32MB and the Colorlight board has only 4MB. So that would be fine to run smaller OSes (like Zephyr), but Linux would need footprint optimization and i'm not sure would be really useful since the FPGA is not very big.

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Hello Florent..

Many thanks for the bitstream and the pointers... Seems like the Ethernet in my laptop had driver issues and was not negotiating at 1Gbps. Tried it on my desktop and managed to get the Litex Bios prompt!

Having said that, I'm not able to interact with the terminal -it just hangs. Also it is non-responsive when I break and restart the RemoteClient code. I have to flash the svf again, restart lxserver and RemoteClient once again to get the prompt - still non-interactive.

I also noticed the timing errors during the nextpnr-ecp5 task:

Warning: Max frequency for clock              '$glbnet$main_crg_clkout': 40.69 MHz (FAIL at 125.00 MHz)
Warning: Max frequency for clock '$glbnet$eth_clocks0_rx$TRELLIS_IO_IN': 96.79 MHz (FAIL at 125.00 MHz)

I understand something needs to be done with datawidth extensions. Are there any tasks at hand with regard to that, probably which you can guide through ?

Finally, I would like to know your feedback on running Linux (even if not full-fledged, some microvariant) on the board. I read around about the limitations with regarding to SDRAM, but nothing concrete. Is it worth opening a separate issue here or on the linux-on-litex repos ?

Cheers

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Once again thanks for the quick response! My bad, I'd noticed in the passing that RemoteClient was doing read-only ;( and now it's all looking good !!

I'll keep playing with this for a while to familiarize with the LiteX SoC modules and see where it can be taken forward...

Planning to do the mods for making IO bidirectional... Bidirectional IO Hack ... Probably then we can mod LiteScope for doing some fast logic analysis over GigE :)

Cheers

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