Comments (6)
pdp7
commented on July 18, 2024
I have run:
pdp7@x1:~/dev/upstream$ sudo ./litex_setup.py update
[updating migen]...
Already up to date.
[updating litex]...
Already up to date.
[updating liteeth]...
Already up to date.
[updating litedram]...
Already up to date.
[updating litepcie]...
Already up to date.
[updating litesata]...
Already up to date.
[updating litesdcard]...
Already up to date.
[updating liteiclink]...
Already up to date.
[updating litevideo]...
Already up to date.
[updating litescope]...
Already up to date.
[updating litejesd204b]...
Already up to date.
[updating litex-boards]...
Already up to date.
pdp7@x1:~/dev/upstream$ sudo ./litex_setup.py install
output in gist since it is large
from litex-boards.
pdp7
commented on July 18, 2024
I think I am up-to-date:
~/dev/upstream/./litesdcard
commit 652f9c24c4aa244bf0efdba98b69a491280a8504 (HEAD -> master, origin/master, origin/HEAD)
Author: Florent Kermarrec <[email protected]>
Date: Thu Jan 9 12:28:41 2020 +0100
example: switch cpu to VexRiscv
~/dev/upstream/./liteeth
commit f2b3f7eeb1a68a4db0d9a3315994374c15e46019 (HEAD -> master, origin/master, origin/HEAD)
Author: Florent Kermarrec <[email protected]>
Date: Mon Nov 25 11:43:16 2019 +0100
test: update test_etherbone, use litex.gen.sim for all tests
~/dev/upstream/./litedram
commit 34e6c24d7296aeed6fb71ddc009b357cfc5a82ca (HEAD -> master, origin/master, origin/HEAD)
Author: Florent Kermarrec <[email protected]>
Date: Fri Jan 10 14:27:05 2020 +0100
frontend/wishbone: add write data buffer to avoid stalling wishbone while waiting for wdata.ready
~/dev/upstream/./litescope
commit daf10e9473fb70b3034e0331ef89005661ac04e0 (HEAD -> master, origin/master, origin/HEAD)
Author: Florent Kermarrec <[email protected]>
Date: Mon Dec 2 13:03:02 2019 +0100
examples/make: based on Migen & LiteX
~/dev/upstream/./migen
commit 677ca961b7c0a8273ba4f0f14070180bf54771fa (HEAD -> master, origin/master, origin/HEAD)
Author: Sebastien Bourdeauducq <[email protected]>
Date: Mon Jan 6 16:54:51 2020 +0800
fix previous commit
~/dev/upstream/./litepcie
commit 5fa8d1a263ebd250fdd9b61d66836a80c91d957d (HEAD -> master, origin/master, origin/HEAD)
Author: Florent Kermarrec <[email protected]>
Date: Thu Jan 9 19:12:53 2020 +0100
gen: allow sys_clk_freq definition
~/dev/upstream/./linux-on-litex-vexriscv-prebuilt
commit 484d4931acdb76f811ccb33f7f7ddc7b6104f3f7 (HEAD -> master, origin/master, origin/HEAD)
Merge: 29d8761 5587286
Author: enjoy-digital <[email protected]>
Date: Mon Jan 6 10:52:36 2020 +0100
Merge pull request #3 from zakgi/master
Added Support for Saanlima's Pipistrello LX45
~/dev/upstream/./litejesd204b
commit 7e2f1736332d02218e5d0a79057a6e0533eadece (HEAD -> master, origin/master, origin/HEAD)
Author: Florent Kermarrec <[email protected]>
Date: Mon Nov 18 23:26:34 2019 +0100
link/Aligner: simplify
~/dev/upstream/./litevideo
commit 146d4a73a242f6449682b58de2428cd351297c8d (HEAD -> master, origin/master, origin/HEAD)
Merge: 7328d27 7c24d18
Author: enjoy-digital <[email protected]>
Date: Sun Dec 1 12:22:35 2019 +0100
Merge pull request #26 from FrankBuss/master
minor comments and example code cleanup
~/dev/upstream/./litesata
commit 1e3573b07d382eac50ef764fd839009bf90cb8ce (HEAD -> master, origin/master, origin/HEAD)
Author: Florent Kermarrec <[email protected]>
Date: Tue Jan 7 16:33:16 2020 +0100
phy/a7sataphy: use same OOB clocking than USB3 PIPE
~/dev/upstream/./litex-boards
commit beccf670e510dca481cabfe6d6a13737e89e4a82 (HEAD -> master, origin/master, origin/HEAD)
Author: Florent Kermarrec <[email protected]>
Date: Sat Jan 11 10:46:23 2020 +0100
hadbadge: fix _CRG
~/dev/upstream/./linux-on-litex-vexriscv
commit 8ecfdcd855d42f5b373e28ecc106f8d67fdfd4be (HEAD -> master, origin/master, origin/HEAD)
Author: Florent Kermarrec <[email protected]>
Date: Fri Jan 10 09:42:54 2020 +0100
make.py/de0nano: increase l2_size to 2048, update comment
~/dev/upstream/./liteiclink
commit 51fb491ed29132b275ccff4b9ab1acb1490166b3 (HEAD -> master, origin/master, origin/HEAD)
Author: Florent Kermarrec <[email protected]>
Date: Fri Dec 13 16:01:46 2019 +0100
transceiver/serdes_ecp5: finish removing clock_aligner
~/dev/upstream/./litex
commit f70dd48279cdb54e5da715d4d5f7a743ee2c370d (HEAD -> master, origin/master, origin/HEAD)
Author: Florent Kermarrec <[email protected]>
Date: Fri Jan 10 14:25:46 2020 +0100
bios/sdram: add memspeed
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enjoy-digital
commented on July 18, 2024
It seems you have another version of litex-boards installed somewhere and this is the one that is used, not the one with the updates. Here it's failing, because you don't have 82601ff.
Can you try to corrupt the hadbadge platform or target and make sure it fails? (to be sure you it's really using this one?). If it's not failing, you have too be sure to remove the old litex-boards repository, or reinstall the curent one. If it's failing with the changes, then please add a print(platform.device) the BaseSoC, then we'll see if 82601ff is really applied.
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pdp7
commented on July 18, 2024
Not sure exactly what my issue was, probably that I have too many different clones of litex in my homedir. I cleaned everything out again. And it finally builds again ok. Sorry for the confusion.
from litex-boards.
pdp7
commented on July 18, 2024
I can now build and boot the hadbadge OK.
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mithro
commented on July 18, 2024
@pdp7 - To prevent this type of problem is exactly why litex-buildenv was written.
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