ecpix-5 target sys clk frequency seems wrong 75MHz instead of 100MHz about litex-boards HOT 2 CLOSED

Hi @bvernoux,

the 100MHz clock is indeed the primary clock of the board that is converted to the internal sys_clk through a PLL. The default sys_clk of 75MHz is the one that has been tested with the default configuration (VexRiscv standard CPU, LiteDRAM controller) and that is both functional and passing timings. That's also the sys_clk frequency we have been using on other ECP5 dev boards. 100MHz also seems to be working on hardware (I just tested: ./ecpix5.py --sys-clk-freq=100e6 --build --load) but timing are not fully satisfied:

Warning: Max frequency for clock              '$glbnet$sys_clk': 99.25 MHz (FAIL at 100.00 MHz)
Info: Max frequency for clock          '$glbnet$crg_clkout1': 165.23 MHz (PASS at 25.00 MHz)
Info: Max frequency for clock '$glbnet$clk100$TRELLIS_IO_IN': 388.05 MHz (PASS at 100.00 MHz)

So we could probably increase the frequency a bit but 75MHz seems to be a good compromise for now and gives some timing margin when adding other peripherals.

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I think the question has been answered, closing.

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