Comments (7)
seems we need to manually invoke
add_clk_primitive()
? but so far failing to force it, comes error always
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forced by FORCE to not fail generation but no idea if correctly, if it can work or how to test it now
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mem_map = {
"spiflash": 0x20000000,
}
mem_map.update(SoCCore.mem_map)
def __init__(self, sys_clk_freq=int(100e6), spiflash="spiflash_4x", **kwargs):
platform = te0725.Platform()
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
ident="TE0725", ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.add_csr("spiflash", allow_user_defined=True)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
spiflash_pads = platform.request(spiflash)
self.submodules.spiflash = SpiFlash(
spiflash_pads,
dummy=spiflash_dummy[spiflash],
endianness=self.cpu.endianness)
self.spiflash.add_clk_primitive("xc7");
= compiles to bitstream.. but works?
from litex-boards.
added
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus)
self.add_memory_region(
"spiflash", self.mem_map["spiflash"] | self.shadow_base, 16*1024*1024)
now can see that does not work yet ;) but getting closer..
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ok got some vivado analyzer captures and some data written to flash read back as well. 2 bytes shifted and bit errors during writing, guessed, maybe div=2 was not good idea, and possible need some clock or io timing constraint also, but something is alive :)
from litex-boards.
div=4, dummy=6 SEEMS to work (no timing constraints)
with div=2 the readback was not constant, so must be timing needed for 50mhz spi clock
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seems all working..
from litex-boards.
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