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View Code? Open in Web Editor NEWA FPGA netlist parser and editor for academic use.
A FPGA netlist parser and editor for academic use.
Hi, @litaotju ,
Thanks for your excellent work, but you said there is a 'requirements.txt' in the project, but I did not find such a file in the project. Is there something wrong?
Thanks!
200多个节点的图(S1238),产生的约束条件有2000多个。等到S15850等电路时,产生的Matlab脚本大小已经达到198M左右。
Issue #3 Status:FIXED
方法:将 \去掉,将“.[]” 全替换成 “”
[HDL 9-806] Syntax error near "\P3.N_1616".
["E:/ISE_WORKSPACE/vivado_itc99_netlist/project_1/project_1.srcs/sources_1/imports/test/b22_insert_scan_chain.v":49959]
assign gated\P3.un1_state_5_i = scan_en?1'b1: \P3.un1_state_5_i ;
assign的左值由问题。 名字不应该这么写。
ballast那一篇文章里面讲的是每一个Reg只能有一个扇入 一个扇出,所以才能把Reg变成 arc,然后有前后依赖关系。但是基本的电路图中 Reg是以单个D触发器的形式出现的,所以怎么merge是一个问题?
还有Reg本身的定义好象跟RTL当中的Reg相似,但是又有所不同,RTL当中的REG依赖于多个FD。
在电路中存在GND和VCC prim,他们只有一个输出,可能练到电路当中其他的组合逻辑或者FD上,由于与他们直接相连接的组合逻辑原语在构建cloud_reg_graph的时候,会被视为同一个cloud(去掉FD后的连通分量视为一个小cloud)。所以在构建cloud_reg_graph时,既要去掉FD,也去掉VCC GND。
重构 circuit.port 类, 增加 port_type的限制之后,将大部分地方进行了同步修改,但是难免有一些地方还有遗漏。需要及时的进行修补。
问题:对于un_opt_ce_list里面的信号,wire区域的声明数量要少于assign区域的数量
有些 gated_ce_signal,在结尾处有assign,但是在wire声明区不存在。
诊断:len(un_opt_ce_list) == 13, len(gated_ce_list) ==3,所以有10个信号没有走相应的分支,gated的修改
是因为修改FDCE使能端口的elif 前面的分支语句已经走过了。所以有的FD并没有走这个分支。
所以造成了少wire声明。
解决方案:重新建立一个循环,查找每一个带有 un_opt_ce_signal的FD。前提条件是前面的处理措施,没有对FD
的名字造成任何改变,只是改变了cellref 和port_list
Issue #7 Status:UN_Resolved
问题:scan_chain中直接进行 port_list.insert()的时候,没有更新相应的
port_assign_list. which is 存储各个port_assign.string信息的列表
问题文件:scan_chain_insert.py
Issue #1 Status:FIXED 方法:该NEW_INIT的生成方法
[HDL 9-806] Syntax error near "'h".
["E:/ISE_WORKSPACE/vivado_itc99_netlist/project_1/project_1.srcs/sources_1/imports/test/b22_insert_scan_chain.v":15419]
b22.v
LUT2 \P3.un1_reg0_0_sqmuxa_1_1_RNI70O7 (
.I0(\P3.un1_state_6_0 ),
.I1(\P3.un1_reg0_0_sqmuxa_1_0 ),
.O(\P3.un1_state_6_i )
);
defparam \P3.un1_reg0_0_sqmuxa_1_1_RNI70O7 .INIT=4'h4;
插入扫描链后:
LUT3 \P3.un1_reg0_0_sqmuxa_1_1_RNI70O7 (
.I0( \P3.un1_state_6_0 ) ,
.I1( \P3.un1_reg0_0_sqmuxa_1_0 ) ,
.I2( scan_en ) ,
.O( \P3.un1_state_6_i )
);
defparam \P3.un1_reg0_0_sqmuxa_1_1_RNI70O7 .INIT=8'hF4'h4 ;
问题:.INIT参数的修改有问题。
Error using sdpvar/subsref (line 149)
Subscript indices must either be real positive integers or logicals.
Error in b03 (line 6)
constraints = [...
Error in run (line 63)
evalin('caller', [script ';']);
问题:使用grhtest\b01 ,b17.vm进行ballast实验,发现所有的移除的D触发器都是在FAS那一步移去的,
第二步根本没有电路可以用来做B-structure。并且b17只有4个节点,三条边。
Traceback (most recent call last):
File "C:\Users\litao\Desktop\a.py", line 8, in
nx.write_dot(g, "abc.dot")
File "", line 2, in write_dot
File "C:\Python27\lib\site-packages\networkx\utils\decorators.py", line 220, in _open_file
result = func(_new_args, *_kwargs)
File "C:\Python27\lib\site-packages\networkx\drawing\nx_pydot.py", line 58, in write_dot
P=to_pydot(G)
File "C:\Python27\lib\site-packages\networkx\drawing\nx_pydot.py", line 212, in to_pydot
p=pydot.Node(make_str(n),**str_nodedata)
File "C:\Python27\lib\site-packages\networkx\utils\misc.py", line 103, in make_str
return unicode(str(x), 'unicode-escape')
UnicodeDecodeError: 'unicodeescape' codec can't decode bytes in position 0-1: truncated \UXXXXXXXX escape
succ 改为prec
Issue #2 Status:UN_Resolved
[HDL 9-31] <P1.reg0_28> is already declared.
["E:/ISE_WORKSPACE/vivado_itc99_netlist/project_1/project_1.srcs/sources_1/imports/test/b22_insert_scan_chain.v":25978]
wire [18:0] \P1.reg0_28 ;
LUT5_L \P1.reg0_28 (
.I0( \P1.reg1_16_699_a6_0 ) ,
.I1( \P1.reg0_N_3_mux ) ,
.I2( \P1.reg0_28_tz_1 ) ,
.I3( \P1.t_1[21] ) ,
.I4( \P1.N_1050 ) ,
.LO( \P1.N_2705 )
);
问题:可能是wire的名字和prim的名称有重叠产生的。
Issue #4 Status:FIXED
方法:LUT[1-4]换成 LUT[1-5]
问题:加入使能端口的可利用LUT,在LUT5时不能自动的变成LUT6,
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