The uvm from lidapang

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UVM Examples

SystemVerilog 97.86% Forth 0.97% Fortran 0.35% Tcl 0.07% Coq 0.67% Verilog 0.08%

uvm's Introduction

                                                   README

UVM is a Hardware Verification Language Methodology built on System Verilog and is one of the most popular and leading HVLs used in the industry.

You may download the base class libraries, source code, and reference guide from : Accellera

This repo will host many code examples to illustrate different features and general usage in UVM. Visit ChipVerify to learn more !

Tag	Desc.
factory-override	Example of how to override components by each of the four `set__override_by_` methods
phasing	Example of how phases of each component in a testbench will be executed
reporting	Example of how to use `uvm_info set of macros and `uvm_report_info()` methods
uvm-intro	Does a walkthrough of UVM testbench building by installing components one by one
register-layer	Build a register model and environment, perform read and write accesses
virtual-sequence	Example of how to build and use a virtual sequence without a separate virtual sequencer
virtual-sequencer	Example of how to build and use a virtual sequencer along with a virtual sequence
TLM	Examples related to TLM `get()`, `put()` and other methods
misc	Other miscellaneous examples to show certain features or clarify usage
seq	Examples that explore creation and usage of uvm sequences and sequence items
file-includes	Examples that show a few styles in which files can be arranged and included for compilation
uvm-printer	Shows how to print UVM data objects, and different print format styles

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