libmir / mir-cpuid Goto Github PK

################ Unified Information ################
Cores per CPU: 6
Threads per CPU: 12
------------------ TLB Information ------------------
Instruction TLB:

• • • • • ITLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 64
          Associativity: 4-way associative
          Data TLB:
• • • • • DTLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 64
          Associativity: 4-way associative
          Unified TLB:
• • • • • UTLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 512
          Associativity: 4-way associative
          ----------------- Cache Information -----------------
          Instruction Cache:
• • • • • ICache1: - - - - - - - - - - - - - - - - -
          Cache size = 32 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 8-way associative
          Data Cache:
• • • • • DCache1: - - - - - - - - - - - - - - - - -
          Cache size = 32 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 8-way associative
          Unified Cache:
• • • • • UCache1: - - - - - - - - - - - - - - - - -
          Cache size = 256 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 8-way associative
• • • • • UCache2: - - - - - - - - - - - - - - - - -
          Cache size = 15360 KB
          Line = 64 bytes
          Cores per cache = 6
          Inclusive: true
          Associativity: 20-way associative

################## x86 Information ##################
brand: Intel(R) Xeon(R) CPU E5-2620 0 @ 2.00GHz
vendor: GenuineIntel
virtualVendor: GenuineIntel
virtual: false
vendorIndex: 0x0
virtualVendorIndex: 0x0
brandIndex: 0x0
maxBasicLeaf: 0xD
maxExtendedLeaf: 0x80000008
max7SubLeafs: 0x0
acpi: true
adx: false
aes: true
apic: true
avx: true
avx2: false
avx512bw: false
avx512cd: false
avx512dq: false
avx512er: false
avx512f: false
avx512ifma: false
avx512pf: false
avx512vbmi: false
avx512vl: false
bmi1: false
bmi2: false
clflushLineSize: 0x8
clflushopt: false
clfsh: true
clwb: false
cmov: true
cmpxchg16b: true
cnxt_id: false
cx8: true
dca: true
de: true
deprecates: false
ds: true
ds_cpl: true
dtes64: true
eist: true
extendedFamily: 0x0
extendedModel: 0x2
f16c: false
family: 0x6
fdp_excptn_only: false
fma: false
fpu: true
fsgsbase: false
fxsr: true
hle: false
htt: true
ia32_tsc_adjust: false
initialAPIC: 0x1
intel_pt: false
invpcid: false
maxLogicalProcessors: 0x20
mca: true
mce: true
mmx: true
model: 0xD
monitor: true
movbe: false
mpx: false
msr: true
mtrr: true
ospke: false
osxsave: true
pae: true
pat: true
pbe: true
pcid: true
pclmulqdq: true
pcommit: false
pdcm: true
pge: true
pku: false
popcnt: true
prefetchwt1: false
pse: true
pse36: true
psn: false
rdrand: false
rdseed: false
rdt_a: false
rdt_m: false
rtm: false
sdbg: false
sep: true
sgx: false
sha: false
smap: false
smep: false
smx: true
self_snoop: true
sse: true
sse2: true
sse3: true
sse41: true
sse42: true
ssse3: true
stepping: 0x7
supports: false
therm_monitor: true
therm_monitor2: true
tsc: true
tsc_deadline: true
type: 0x0
vme: true
vmx: true
x2apic: true
xsave: true
xtpr: true

https://gist.github.com/gchatelet/31a8cf41ba1d888c1efaef314d6a0c97

Previously something like:

dub fetch mir-cpuid && dub test mir-cpuid

worked & it was quite convenient way for the users. How about adding a executable target, s.t.

dub fetch mir-cpuid && dub run mir-cpuid

would execute the report? Would you accept a PR?

################ Unified Information ################
Cores per CPU: 4
Threads per CPU: 4
------------------ TLB Information ------------------
Instruction TLB:

• • • • • ITLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 48
          Associativity: Fully associative
• • • • • ITLB2: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 1024
          Associativity: 8-way associative
          Data TLB:
• • • • • DTLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 64
          Associativity: Fully associative
• • • • • DTLB2: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 1024
          Associativity: 8-way associative
          Unified TLB:
          ----------------- Cache Information -----------------
          Instruction Cache:
• • • • • ICache1: - - - - - - - - - - - - - - - - -
          Cache size = 64 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 2-way associative
          Data Cache:
• • • • • DCache1: - - - - - - - - - - - - - - - - -
          Cache size = 16 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 4-way associative
          Unified Cache:
• • • • • UCache1: - - - - - - - - - - - - - - - - -
          Cache size = 2048 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 16-way associative
• • • • • UCache2: - - - - - - - - - - - - - - - - -
          Cache size = 4096 KB
          Line = 64 bytes
          Cores per cache = 4
          Inclusive: false
          Associativity: 32-way associative

################## x86 Information ##################
brand: AMD FX(tm)-4300 Quad-Core Processor
vendor: AuthenticAMD
virtualVendor: AuthenticAMD
virtual: false
vendorIndex: 0x1
virtualVendorIndex: 0x1
brandIndex: 0x0
maxBasicLeaf: 0xD
maxExtendedLeaf: 0x8000001E
max7SubLeafs: 0x0
acpi: false
adx: false
aes: true
apic: true
avx: true
avx2: false
avx512bw: false
avx512cd: false
avx512dq: false
avx512er: false
avx512f: false
avx512ifma: false
avx512pf: false
avx512vbmi: false
avx512vl: false
bmi1: true
bmi2: false
clflushLineSize: 0x8
clflushopt: false
clfsh: true
clwb: false
cmov: true
cmpxchg16b: true
cnxt_id: false
cx8: true
dca: false
de: true
deprecates: false
ds: false
ds_cpl: false
dtes64: false
eist: false
extendedFamily: 0x6
extendedModel: 0x0
f16c: true
family: 0xF
fdp_excptn_only: false
fma: true
fpu: true
fsgsbase: false
fxsr: true
hle: false
htt: true
ia32_tsc_adjust: false
initialAPIC: 0x3
intel_pt: false
invpcid: false
maxLogicalProcessors: 0x4
mca: true
mce: true
mmx: true
model: 0x2
monitor: true
movbe: false
mpx: false
msr: true
mtrr: true
ospke: false
osxsave: true
pae: true
pat: true
pbe: false
pcid: false
pclmulqdq: true
pcommit: false
pdcm: false
pge: true
pku: false
popcnt: true
prefetchwt1: false
pse: true
pse36: true
psn: false
rdrand: false
rdseed: false
rdt_a: false
rdt_m: false
rtm: false
sdbg: false
sep: true
sgx: false
sha: false
smap: false
smep: false
smx: false
self_snoop: false
sse: true
sse2: true
sse3: true
sse41: true
sse42: true
ssse3: true
stepping: 0x0
supports: false
therm_monitor: false
therm_monitor2: false
tsc: true
tsc_deadline: false
type: 0x0
vme: true
vmx: false
x2apic: false
xsave: true
xtpr: false

@wilzbach Could you fix it please

################ Unified Information ################
Cores per CPU: 4
Threads per CPU: 8
------------------ TLB Information ------------------
Instruction TLB:

• • • • • ITLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 128
          Associativity: 4-way associative
          Data TLB:
• • • • • DTLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 64
          Associativity: 4-way associative
          Unified TLB:
• • • • • UTLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 512
          Associativity: 4-way associative
          ----------------- Cache Information -----------------
          Instruction Cache:
• • • • • ICache1: - - - - - - - - - - - - - - - - -
          Cache size = 32 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 4-way associative
          Data Cache:
• • • • • DCache1: - - - - - - - - - - - - - - - - -
          Cache size = 32 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 8-way associative
          Unified Cache:
• • • • • UCache1: - - - - - - - - - - - - - - - - -
          Cache size = 256 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 8-way associative
• • • • • UCache2: - - - - - - - - - - - - - - - - -
          Cache size = 8192 KB
          Line = 64 bytes
          Cores per cache = 4
          Inclusive: true
          Associativity: 16-way associative

################## x86 Information ##################
brand: Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz
vendor: GenuineIntel
virtualVendor: GenuineIntel
virtual: false
vendorIndex: 0x0
virtualVendorIndex: 0x0
brandIndex: 0x0
maxBasicLeaf: 0xB
maxExtendedLeaf: 0x80000008
max7SubLeafs: 0x0
acpi: true
adx: false
aes: false
apic: true
avx: false
avx2: false
avx512bw: false
avx512cd: false
avx512dq: false
avx512er: false
avx512f: false
avx512ifma: false
avx512pf: false
avx512vbmi: false
avx512vl: false
bmi1: false
bmi2: false
clflushLineSize: 0x8
clflushopt: false
clfsh: true
clwb: false
cmov: true
cmpxchg16b: true
cnxt_id: false
cx8: true
dca: false
de: true
deprecates: false
ds: true
ds_cpl: true
dtes64: true
eist: true
extendedFamily: 0x0
extendedModel: 0x1
f16c: false
family: 0x6
fdp_excptn_only: false
fma: false
fpu: true
fsgsbase: false
fxsr: true
hle: false
htt: true
ia32_tsc_adjust: false
initialAPIC: 0x6
intel_pt: false
invpcid: false
maxLogicalProcessors: 0x10
mca: true
mce: true
mmx: true
model: 0xA
monitor: true
movbe: false
mpx: false
msr: true
mtrr: true
ospke: false
osxsave: false
pae: true
pat: true
pbe: true
pcid: false
pclmulqdq: false
pcommit: false
pdcm: true
pge: true
pku: false
popcnt: true
prefetchwt1: false
pse: true
pse36: true
psn: false
rdrand: false
rdseed: false
rdt_a: false
rdt_m: false
rtm: false
sdbg: false
sep: true
sgx: false
sha: false
smap: false
smep: false
smx: false
self_snoop: true
sse: true
sse2: true
sse3: true
sse41: true
sse42: true
ssse3: true
stepping: 0x5
supports: false
therm_monitor: true
therm_monitor2: true
tsc: true
tsc_deadline: false
type: 0x0
vme: true
vmx: true
x2apic: false
xsave: false
xtpr: true

cast(ushort) _cpuid(0xB, 0).b returns 0 on RackSpace/appveyor for
Vendor: GenuineIntel
Brand: Intel(R) Xeon(R) CPU E5-2680 v3 @ 2.50GHz

I tried following the instructions on the mir-glas page to build mir-cpuid on Windows 7.

I have ldc 1.2.0 installed and Microsoft Visual Studio 2017 Community installed. However, when I run the code (with or without the --arch statement), then I get the result below. At the "Warning: Unknown switch 'out' in command line, ignored." part I just hit enter to continue.

If I change --compiler=dmd, then it builds with no errors.

C:\ProgrammingFiles\DFiles\dubFolder\mir-cpuid-0.5.2>dub build --build=release-n
obounds --compiler=ldmd2 --build-mode=singleFile --parallel --force --arch=x86_6
4
The determined compiler type "ldc" doesn't match the expected type "dmd". This w
ill probably result in build errors.
Performing "release-nobounds" build using ldmd2 for x86_64.
mir-cpuid 0.5.2: building configuration "library"...
Compiling source\cpuid\amd.d...
Compiling source\cpuid\amd.d...
Compiling source\cpuid\common.d...
Compiling source\cpuid\intel.d...
Compiling source\cpuid\unified.d...
Compiling source\cpuid\x86_any.d...
Linking...
Using Visual C++: C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC
The specified configuration type is missing. The tools for the
configuration might not be installed.
Digital Mars Librarian Version 8.02n
Copyright (C) Digital Mars 2000-2007 All Rights Reserved
http://www.digitalmars.com/ctg/lib.html
Warning: Unknown switch 'out' in command line, ignored.
list file (.lst)
output library file (.lib)

Warning: 'release.obj' not found, can't delete or extract it
Warning: 'nobounds.obj' not found, can't delete or extract it
Warning: 'windows.obj' not found, can't delete or extract it
Warning: 'x86_64.obj' not found, can't delete or extract it
Warning: 'ldc_2072.obj' not found, can't delete or extract it
Warning: '627BF58E3EFA637A1F171B259BC1D9E6\mir.obj' not found, can't delete or e
xtract it
Warning: 'cpuid.lib' not found, can't delete or extract it

Error: .dub\build\library.obj : No such file or directory
Error: C:\Windows\system32\cmd.exe /s /c "C:\D\ldc\ldc2-1.2.0-win64-msvc\bin\am d64.bat lib.exe" failed with status: 1
ldmd2 failed with exit code 1.

################ Unified Information ################
Cores per CPU: 4
Threads per CPU: 4
------------------ TLB Information ------------------
Instruction TLB:

• • • • • ITLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 128
          Associativity: 4-way associative
          Data TLB:
• • • • • DTLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 64
          Associativity: 4-way associative
          Unified TLB:
• • • • • UTLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 512
          Associativity: 4-way associative
          ----------------- Cache Information -----------------
          Instruction Cache:
• • • • • ICache1: - - - - - - - - - - - - - - - - -
          Cache size = 32 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 8-way associative
          Data Cache:
• • • • • DCache1: - - - - - - - - - - - - - - - - -
          Cache size = 32 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 8-way associative
          Unified Cache:
• • • • • UCache1: - - - - - - - - - - - - - - - - -
          Cache size = 256 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 8-way associative
• • • • • UCache2: - - - - - - - - - - - - - - - - -
          Cache size = 6144 KB
          Line = 64 bytes
          Cores per cache = 4
          Inclusive: true
          Associativity: 12-way associative

################## x86 Information ##################
brand: Intel(R) Core(TM) i5-3470 CPU @ 3.20GHz
vendor: GenuineIntel
virtualVendor: GenuineIntel
virtual: false
vendorIndex: 0x0
virtualVendorIndex: 0x0
brandIndex: 0x0
maxBasicLeaf: 0xD
maxExtendedLeaf: 0x80000008
max7SubLeafs: 0x0
acpi: true
adx: false
aes: true
apic: true
avx: true
avx2: false
avx512bw: false
avx512cd: false
avx512dq: false
avx512er: false
avx512f: false
avx512ifma: false
avx512pf: false
avx512vbmi: false
avx512vl: false
bmi1: false
bmi2: false
clflushLineSize: 0x8
clflushopt: false
clfsh: true
clwb: false
cmov: true
cmpxchg16b: true
cnxt_id: false
cx8: true
dca: false
de: true
deprecates: false
ds: true
ds_cpl: true
dtes64: true
eist: true
extendedFamily: 0x0
extendedModel: 0x3
f16c: true
family: 0x6
fdp_excptn_only: false
fma: false
fpu: true
fsgsbase: true
fxsr: true
hle: false
htt: true
ia32_tsc_adjust: false
initialAPIC: 0x2
intel_pt: false
invpcid: false
maxLogicalProcessors: 0x10
mca: true
mce: true
mmx: true
model: 0xA
monitor: true
movbe: false
mpx: false
msr: true
mtrr: true
ospke: false
osxsave: true
pae: true
pat: true
pbe: true
pcid: true
pclmulqdq: true
pcommit: false
pdcm: true
pge: true
pku: false
popcnt: true
prefetchwt1: false
pse: true
pse36: true
psn: false
rdrand: true
rdseed: false
rdt_a: false
rdt_m: false
rtm: false
sdbg: false
sep: true
sgx: false
sha: false
smap: false
smep: true
smx: true
self_snoop: true
sse: true
sse2: true
sse3: true
sse41: true
sse42: true
ssse3: true
stepping: 0x9
supports: true
therm_monitor: true
therm_monitor2: true
tsc: true
tsc_deadline: true
type: 0x0
vme: true
vmx: true
x2apic: true
xsave: true
xtpr: true

Needs AMD leaf 8 information.

################ Unified Information ################
Cores per CPU: 3
Threads per CPU: 4
------------------ TLB Information ------------------
Instruction TLB:

• • • • • ITLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 128
          Associativity: 4-way associative
          Data TLB:
• • • • • DTLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 16
          Associativity: 4-way associative
• • • • • DTLB2: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 256
          Associativity: 4-way associative
          Unified TLB:
          ----------------- Cache Information -----------------
          Instruction Cache:
• • • • • ICache1: - - - - - - - - - - - - - - - - -
          Cache size = 32 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 8-way associative
          Data Cache:
• • • • • DCache1: - - - - - - - - - - - - - - - - -
          Cache size = 32 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 8-way associative
          Unified Cache:
• • • • • UCache1: - - - - - - - - - - - - - - - - -
          Cache size = 4096 KB
          Line = 64 bytes
          Cores per cache = 3
          Inclusive: false
          Associativity: 16-way associative

################## x86 Information ##################
brand: Intel(R) Xeon(R) CPU X5365 @ 3.00GHz
vendor: GenuineIntel
virtualVendor: GenuineIntel
virtual: false
vendorIndex: 0x0
virtualVendorIndex: 0x0
brandIndex: 0x0
maxBasicLeaf: 0xA
maxExtendedLeaf: 0x80000008
max7SubLeafs: 0x0
acpi: true
adx: false
aes: false
apic: true
avx: false
avx2: false
avx512bw: false
avx512cd: false
avx512dq: false
avx512er: false
avx512f: false
avx512ifma: false
avx512pf: false
avx512vbmi: false
avx512vl: false
bmi1: false
bmi2: false
clflushLineSize: 0x8
clflushopt: false
clfsh: true
clwb: false
cmov: true
cmpxchg16b: true
cnxt_id: false
cx8: true
dca: true
de: true
deprecates: false
ds: true
ds_cpl: true
dtes64: true
eist: true
extendedFamily: 0x0
extendedModel: 0x0
f16c: false
family: 0x6
fdp_excptn_only: false
fma: false
fpu: true
fsgsbase: false
fxsr: true
hle: false
htt: true
ia32_tsc_adjust: false
initialAPIC: 0x3
intel_pt: false
invpcid: false
maxLogicalProcessors: 0x4
mca: true
mce: true
mmx: true
model: 0xF
monitor: true
movbe: false
mpx: false
msr: true
mtrr: true
ospke: false
osxsave: false
pae: true
pat: true
pbe: true
pcid: false
pclmulqdq: false
pcommit: false
pdcm: true
pge: true
pku: false
popcnt: false
prefetchwt1: false
pse: true
pse36: true
psn: false
rdrand: false
rdseed: false
rdt_a: false
rdt_m: false
rtm: false
sdbg: false
sep: true
sgx: false
sha: false
smap: false
smep: false
smx: false
self_snoop: true
sse: true
sse2: true
sse3: true
sse41: false
sse42: false
ssse3: true
stepping: 0xB
supports: false
therm_monitor: true
therm_monitor2: true
tsc: true
tsc_deadline: false
type: 0x0
vme: true
vmx: true
x2apic: false
xsave: false
xtpr: true

################ Unified Information ################
Cores per CPU: 2
Threads per CPU: 4
------------------ TLB Information ------------------
Instruction TLB:

• • • • • ITLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 64
          Associativity: 8-way associative
          Data TLB:
• • • • • DTLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 64
          Associativity: 4-way associative
          Unified TLB:
• • • • • UTLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 1536
          Associativity: 6-way associative
          ----------------- Cache Information -----------------
          Instruction Cache:
• • • • • ICache1: - - - - - - - - - - - - - - - - -
          Cache size = 32 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 8-way associative
          Data Cache:
• • • • • DCache1: - - - - - - - - - - - - - - - - -
          Cache size = 32 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 8-way associative
          Unified Cache:
• • • • • UCache1: - - - - - - - - - - - - - - - - -
          Cache size = 256 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 4-way associative
• • • • • UCache2: - - - - - - - - - - - - - - - - -
          Cache size = 3072 KB
          Line = 64 bytes
          Cores per cache = 2
          Inclusive: true
          Associativity: 12-way associative

################## x86 Information ##################
brand: Intel(R) Core(TM) i3-6100U CPU @ 2.30GHz
vendor: GenuineIntel
virtualVendor: GenuineIntel
virtual: false
vendorIndex: 0x0
virtualVendorIndex: 0x0
brandIndex: 0x0
maxBasicLeaf: 0x16
maxExtendedLeaf: 0x80000008
max7SubLeafs: 0x0
acpi: true
adx: true
aes: true
apic: true
avx: true
avx2: true
avx512bw: false
avx512cd: false
avx512dq: false
avx512er: false
avx512f: false
avx512ifma: false
avx512pf: false
avx512vbmi: false
avx512vl: false
bmi1: true
bmi2: true
clflushLineSize: 0x8
clflushopt: true
clfsh: true
clwb: false
cmov: true
cmpxchg16b: true
cnxt_id: false
cx8: true
dca: false
de: true
deprecates: true
ds: true
ds_cpl: true
dtes64: true
eist: true
extendedFamily: 0x0
extendedModel: 0x4
f16c: true
family: 0x6
fdp_excptn_only: false
fma: true
fpu: true
fsgsbase: true
fxsr: true
hle: true
htt: true
ia32_tsc_adjust: true
initialAPIC: 0x0
intel_pt: true
invpcid: true
maxLogicalProcessors: 0x10
mca: true
mce: true
mmx: true
model: 0xE
monitor: true
movbe: true
mpx: true
msr: true
mtrr: true
ospke: false
osxsave: true
pae: true
pat: true
pbe: true
pcid: true
pclmulqdq: true
pcommit: false
pdcm: true
pge: true
pku: false
popcnt: true
prefetchwt1: false
pse: true
pse36: true
psn: false
rdrand: true
rdseed: true
rdt_a: false
rdt_m: false
rtm: true
sdbg: true
sep: true
sgx: true
sha: false
smap: true
smep: true
smx: false
self_snoop: true
sse: true
sse2: true
sse3: true
sse41: true
sse42: true
ssse3: true
stepping: 0x3
supports: true
therm_monitor: true
therm_monitor2: true
tsc: true
tsc_deadline: true
type: 0x0
vme: true
vmx: true
x2apic: true
xsave: true
xtpr: true

################ Unified Information ################
Cores per CPU: 4
Threads per CPU: 8
------------------ TLB Information ------------------
Instruction TLB:

• • • • • ITLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 64
          Associativity: 4-way associative
          Data TLB:
• • • • • DTLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 64
          Associativity: 4-way associative
          Unified TLB:
• • • • • UTLB1: - - - - - - - - - - - - - - - - - -
          Page size = 4 KB
          Pages count = 512
          Associativity: 4-way associative
          ----------------- Cache Information -----------------
          Instruction Cache:
• • • • • ICache1: - - - - - - - - - - - - - - - - -
          Cache size = 32 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 4-way associative
          Data Cache:
• • • • • DCache1: - - - - - - - - - - - - - - - - -
          Cache size = 32 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 8-way associative
          Unified Cache:
• • • • • UCache1: - - - - - - - - - - - - - - - - -
          Cache size = 256 KB
          Line = 64 bytes
          Cores per cache = 1
          Inclusive: false
          Associativity: 8-way associative
• • • • • UCache2: - - - - - - - - - - - - - - - - -
          Cache size = 8192 KB
          Line = 64 bytes
          Cores per cache = 4
          Inclusive: true
          Associativity: 16-way associative

################## x86 Information ##################
brand: Intel(R) Xeon(R) CPU X3450 @ 2.67GHz
vendor: GenuineIntel
virtualVendor: GenuineIntel
virtual: false
vendorIndex: 0x0
virtualVendorIndex: 0x0
brandIndex: 0x0
maxBasicLeaf: 0xB
maxExtendedLeaf: 0x80000008
max7SubLeafs: 0x0
acpi: true
adx: false
aes: false
apic: true
avx: false
avx2: false
avx512bw: false
avx512cd: false
avx512dq: false
avx512er: false
avx512f: false
avx512ifma: false
avx512pf: false
avx512vbmi: false
avx512vl: false
bmi1: false
bmi2: false
clflushLineSize: 0x8
clflushopt: false
clfsh: true
clwb: false
cmov: true
cmpxchg16b: true
cnxt_id: false
cx8: true
dca: false
de: true
deprecates: false
ds: true
ds_cpl: true
dtes64: true
eist: true
extendedFamily: 0x0
extendedModel: 0x1
f16c: false
family: 0x6
fdp_excptn_only: false
fma: false
fpu: true
fsgsbase: false
fxsr: true
hle: false
htt: true
ia32_tsc_adjust: false
initialAPIC: 0x3
intel_pt: false
invpcid: false
maxLogicalProcessors: 0x10
mca: true
mce: true
mmx: true
model: 0xE
monitor: true
movbe: false
mpx: false
msr: true
mtrr: true
ospke: false
osxsave: false
pae: true
pat: true
pbe: true
pcid: false
pclmulqdq: false
pcommit: false
pdcm: true
pge: true
pku: false
popcnt: true
prefetchwt1: false
pse: true
pse36: true
psn: false
rdrand: false
rdseed: false
rdt_a: false
rdt_m: false
rtm: false
sdbg: false
sep: true
sgx: false
sha: false
smap: false
smep: false
smx: true
self_snoop: true
sse: true
sse2: true
sse3: true
sse41: true
sse42: true
ssse3: true
stepping: 0x5
supports: false
therm_monitor: true
therm_monitor2: true
tsc: true
tsc_deadline: false
type: 0x0
vme: true
vmx: true
x2apic: false
xsave: false
xtpr: true

I powered up my old IBM T23 from around 2000, thinking that it would be an excellent test case: https://gist.github.com/mleise/4ed5637371ca5cea07bef8241adc7d80
Some thought food: The T23 is an ACPI system with local APIC and all the modern plug&play stuff, yet CPUID reports false for these features. This can lead to confusion, especially when with the addition of ARM support "CPUID" is only one backend of many and information may be acquired by "any means necessary". For example acpi does not return whether the CPU is usable in and supports an ACPI system, but whether "the processor implements internal MSRs that allow processor temperature to be monitored and processor performance to be modulated in predefined duty cycles under software control", which may apply to ARM as well, just not under the wrap of ACPI. I wonder if the library should be called "cpuinfo" and some of those flags should instead be named cpuidAcpi or Cpuid.acpi() and similar and only be available on X86.

On request I provide information for a Core(TM) i5-4200U CPU @ 1.60GHz, too. But it's just another mobile Haswell.