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#Vim Syntax Plugin for Verilog and SystemVerilog

Based on script originally found at:

http://www.vim.org/scripts/script.php?script_id=1586

Besides some bug corrections, the following features were added to this set of scripts:

• Omni completion.
• Configurable syntax folding.
• Updated matchit configurations to properly support Verilog 2001 and SystemVerilog.
• Error format definitions for common Verilog tools.
• Commands for following instances.
• Automatically enabled for the following file extensions: .v.vh.sv.svi.svh

This plugin implements an omni completion function that will offer completion suggestions depending on the current context. This will only work if a . character is found in the keyword behind the cursor. At the moment the following contexts are supported:

1. Module instantiation port names.
2. Function/task arguments.
3. Object methods and attrtibutes.

In order to use omni completion a tags file must be generated using the following arguments:

• --extra=+q - Enable hierarchy qualified tags extraction.
• --fields=+i - Enable class inheritance extraction.
• -n - (Optional) Use line number instead of Ex: patterns to identify declaration.

No tool alternative to exuberant-ctags was tested, but any tool should work seemingly as long as it is able to generate a standard class qualified tags file. For more information on using omni completion please check the vim man page for i_CTRL-X_CTRL-O (the required option omnifunc is automatically defined for the supported file extensions).

TODO: Explain how gd works

Note: Proper SystemVerilog tag generation requires development version of exuberant-ctags.

To enable syntax folding set the following option:

set foldmethod=syntax

This plugin includes the errorformat configurations for the following Verilog tools:

• Synopsys VCS (vcs)
• Mentor Modelsim (msim)
• Icarus Verilog (iverilog)
• GPL Cver (cver)
• Synopsys Leda (leda)

The command VerilogErrorFormat allows the interactive selection of these configurations. In some cases it is also possible to ignore lint and/or warning level messages.

A specific tool can be directly selected calling this command with some arguments. Below is an example for VCS:

VerilogErrorFormat vcs 2

In this example the second argument disables the detection of lint messages. This argument can take the following values:

1. All messages are detected.
2. Ignore lint messages.
3. Ignore lint and warning messages.

After the errorformat has been so defined, it is only a matter of setting makeprg and run :make to call the tool of choice and vim will automatically detect errors, open the required file and place the cursor on the error position. To navigate the error list use the commands :cnext and :cprevious.

For more information check the help page for the quickfix vim feature.

A framework is provided to follow a module instance to its module declaration as long as its respective entry exists in the tags file. To do so simply execute :VerilogFollowInstance within the instance to follow it to its declaration.

Alternatively, if the cursor is placed over a port of the instance the command :VerilogFollowPort can be used to navigate to the module declaration and immediately searching for that port.

These commands can be mapped as following:

nnoremap <leader>i :VerilogFollowInstance<CR>
nnoremap <leader>I :VerilogFollowPort<CR>

The command :VerilogGotoInstanceStart is provided to move the cursor to the start of the first module instantiation that precedes the current cursor location.

This command can be mapped as following:

nnoremap <leader>u :VerilogGotoInstanceStart<CR>

1. Add the following to your vimrc:

Plug 'vhda/verilog_systemverilog.vim'

2. Run:

vim +PlugInstall +qall

1. Add the following to your vimrc:

Plugin 'vhda/verilog_systemverilog.vim' 2. Run:

vim +PluginInstall +qall

1. cd ~/.vim/bundle
2. git clone https://github.com/vhda/verilog_systemverilog.vim

• b:verilog_indent_width - Use this variable to override the option &shiftwidth.

• b:verilog_indent_modules - Indent code after module declaration.

• b:g:verilog_dont_deindent_eos - Keep last ) of module port declaration indented.

• g:verilog_syntax_fold - Enable verilog syntax folding. Comma separated list containing one or more of the following values:

  • function
  • task
  • specify
  • covergroup
  • sequence
  • property
  • specify
  • block (begin, end)
  • comment (/*..*/)
  • define (`ifdef,`ifndef, `elsif, `else, `endif)
  • all (enables all above options)

  Set to an empty string to disable syntax folding.

• b:verilog_indent_verbose - Verbose indenting (uses echom).
• b:verilog_omni_verbose - Verbose omni completion (uses echom).

This addon allows using % to jump between matching keywords as Vim already does for matching parentheses/brackets. Many syntax files include the definition of the matching keyword pairs for their supported languages.

Since it is already included in all Vim installations and the addon can be easily loaded by adding the following line to .vimrc:

runtime macros/matchit.vim

The hl_matchit.vim addon complements Matchit by automatically underlining matching words, similarly as Vim already does for parentheses/brackets.

Supertab configures the tab key to perform insert completion. To take full advantage of the omni completion functionality the following configuration should be used:

let g:SuperTabDefaultCompletionType = "context"

When this is done Supertab will choose the most appropriate type of completion to use depending on the current context.

Tagbar allows browsing all variable, functions, tasks, etc within a file in a nice hierarchical view. SystemVerilog language and Verilog/SystemVerilog hierarchical browsing are only supported when used together with the development version of exuberant-ctags.

The required filetype related configuration for Tagbar is included within this addon.