TinyTapeout is an educational project that aims to make it easier and cheaper than ever to get your digital designs manufactured on a real chip.

To learn more and get started, visit https://tinytapeout.com.

Edit the info.yaml and change the wokwi_id to the ID of your Wokwi project. You can find the ID in the URL of your project, it's the big number after wokwi.com/projects/.

The GitHub action will automatically fetch the digital netlist from Wokwi and build the ASIC files.

Edit the info.yaml and uncomment the source_files and top_module properties, and change the value of language to "Verilog". Add your Verilog files to the src folder, and list them in the source_files property.

The GitHub action will automatically build the ASIC files using OpenLane.

Please see the instructions for:

• Enabling GitHub Actions
• Enabling GitHub Pages

• FAQ
• Digital design lessons
• Learn how semiconductors work
• Join the community

• Submit your design to the next shuttle on the website. The closing date is November 4th.
• Edit this README and explain your design, how it works, and how to test it.
• Share your GDS on your social network of choice, tagging it #tinytapeout and linking Matt's profile:
  • LinkedIn #tinytapeout matt-venn
  • Mastodon #tinytapeout @matthewvenn
  • Twitter #tinytapeout @matthewvenn