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datalogger's Issues

Arbitrary Sample Rates

Change dropdown to a combo box so users can type in any sample rate their heart desires, with SI suffixes.

Addressing is broken

SOme very confusing issues with addressing. Firstly in the retrieve no addressing seems to be taking place at all. No clocks to the counter, no counting, as far as I can see no calls to writeRAM. Also in the capture phase A16 (0 based) is toggling at 23Hz, which is silly fast considering it should take a good while to fill half the RAM. I dunno what on earth's up.

Analyser confused if capture cancelled

Say the user hits the UI reconnect command while a capture/retrieve is in progress - things go horribly wrong, analyser doesn't respond to pings, etc. Not sure if can be bothered to fix.

Update schematic

Add hysteresis
Make all buses 0-based numbered
Swap pinout order on latch
Set LE high, not low, on latch
Make us have 8 Vrefs, not 1, and change R values
Add filter values

Trigger byte to begin sampling

Begin sampling on a particular trigger byte - done by reading the shift reg as fast as possible to read the data lines. Could be done on either async or sync capture mode.

Samplenumber is wrong

Pretty sure the firmware is at fault with this one. I Just put code in to give me the entire packet length (returned from the USB function given) inc headers and everything. For 100 samples, I get packet lengths 64 and 39, giving payloads length 62+37=99, the actual data length received.

Similarly, with 200 samples, I get packet lengths 64, 64, 64, 13, payloads 62+62+62+11 = 197, the actual number of samples received.

Test UI with wait before capture

So far have only tested software/UI with instant asynchronous capture - need to check it works with the arming / waiting for clock stage.

Synchronous estimated clock rate

Measure/estimate synchronous clock rate - use a spare timer on the PIC? Then return it, say as a payload to the finished capture command or something and display in UI. UI can give estimated time from 0 datum of each sample.

Async capture rates <100Hz

Would need to change config setup - could use an unused OPT bit to divide rate by 1,000,000 or invert or something.

Would need software scalers for <100Hz

Optimise RAM write cycle

Specifically, do we need to release from standby at the start and go back in at the end? Or will it tolerate burst writes?

Who knows.

Data retrieval code

Respond to PC commands for getting data, and read it out of RAM and transmit using the appropriate control codes

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