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Hi there, I'm Johan

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  • 💻 I’m interested in FPGA Digital Design, HPC Software Dev and Computer Architecture.
    • FPGAs : Latency/Throughput driven designs, Resource/Target Aware Neural Network mappings, Custom Mathematical Function Acceleration.
    • HPC Software : Concurrency, Distributed Systems, Parallel computing (Using GPUs, SIMD Vectorisation, Software to ASIC)
    • Computer Arch : Hardware Aware Compiler Optimisations, Profile Guided Optimisations, Application Specific CPU/SoC Design (Ex: Tesla Dojo, Signal Processing MCUs/DSPs)
  • 📚 Experienced Languages: C/C++, Python, SystemVerilog/Verilog, Maxeler (Hardware Design DSL), Bash
  • 🔬 Experienced Tools: Intel Quartus, Intel VTune Profiler, Perf, Docker, Kubernetes, PyTorch/TensorFlow, Verilator/ModelSim.
  • 🌱 Love reading science and medicine just to know more about who I am 👨, where we are 🌍 and where we can go 🚀.
  • 📫 Reach me out for any questions!

GitHub Stats :



Johan Jino's Projects

execengine_c_compiler icon execengine_c_compiler

ANSI C to RISC-V assembly compiler as part of the EIE 2nd Year Instruction Set Architecture and Compilers coursework.

flappyga icon flappyga

Online Multiplayer Flappy Birds Game developed with controls on FPGA embedded accelerometer

lab2-siggen icon lab2-siggen

2nd Lab Instruction - Signal Generation and Capture

lab3-fsm icon lab3-fsm

Lab 3 is all about designing finite state machines

mazemaster icon mazemaster

Autonomous bot capable of balancing on two wheels that traverses through a maze formed using white LED strips and maps it on a webapp to find shortest path. This project was developed as part of the engineering design project for 2nd year EIE.

nmos-cpp icon nmos-cpp

An NMOS (Networked Media Open Specifications) Registry and Node in C++ (IS-04, IS-05)

risc-v_cpu icon risc-v_cpu

RISC-V 32I CPU designed as part of the instruction set architecture (ISA) module for 2nd year EIE at Imperial College London.

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