reorder bits or #2

less eficient code, probably nicer to setup thread stack (and u mode) #5

rv32e has a large gap here

• certain ranges only
• certain nesting levels only
• whole regfile
• etc

requires extra mechanism to access shadowed registers

register content upon irq entry implementation specified

push/pop of remaining integer and fp registers through a0/a1 as base

#26 no more necessary
Requires additional csrrw (atomic swap for precomputed next TCB, 2 for typical way), no overhead (or -1 for atomic swap) when no shadow regs are present

use integrity/illegal instr ones

frees 1 NMI vector entry

more consistent with current definitions used all over the standard extensions

move a6,a7 to x20,x21 and add x22,x23 as temporaries

no longer aligns with standard zcmp[e] reglist.
extra temporaries shouldn't have negative impact wrt IPRA

ARM synchronizes only cpsid i.
According to freeRTOS writes to basepri are also not synchronized

reduce bits for addressing, reduce contention with other custom extensions

?

needs to be an NMI
in thread state only

some signals forwarded to "external" irq controller #20, #13

instead of lazy stacking for higher efficiency.

executed after stacking of integer registers amortized irq entry overhead

unlike other gpr registers, sp can be operated by cm.push/cm.pop/c.*sp instructions

cannot swap sp with teic_swpspm due to nesting

as optional ext

loses straightoforward "increase level only by csrsi/csrci" feature.

total 5, priority + nesting priority bits possible by csrwi

24 vs 32 bit counter

?

in software

ensure there is no race cond

hidden state to track if only n4 occured?

what should be a naming for privileged/volume II replacement

unrecoverable, exceptions, other returnable + reserved for startup

psABI makes it a mirror of integer, reshuffle for more efficient #10/IPRA