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View Code? Open in Web Editor NEWscratchip is a framework that can help to build your Chisel and Verilog/Systemverilog project easier.
License: Apache License 2.0
scratchip is a framework that can help to build your Chisel and Verilog/Systemverilog project easier.
License: Apache License 2.0
Request a feature? Please fill out the sections below.
project.yml
should always be created when we run scratchip create PROJ
, the project.yml should include everything for re-init the project. Also, a version should be specified to make it's easy to upgrade to new version.
# contents of project.yml
version: 0.2.1
filelist:
rtl:
- include
- rtl/verilog/ethmac.v
- rtl/verilog/eth_clkgen.v
sim:
- inlucde: rtl
syn:
- include: rtl
fpga:
- include: rtl
scratchip filelist
Impact: unknown
Development Phase: proposal
Please release the Makefile mentioned in "build scratchip from scratch".
Build file release.
no functional change
request
Refer to how-to-build
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