Functional verification project for the CORE-V family of RISC-V cores. This project is under active development.

The OpenHW Group CV32E40P is now live!
This repository no longer contains a local copy of the RTL. The RTL is cloned from the appropriate core-v-cores repository as needed. The specific branch and hash of the RTL is controlled by a set of variables in cv32/sim/Common.mk.

First, have a look at the OpenHW Group's website to learn a bit more about who we are and what we are doing.

The design and verification documentation for the various CORE-V cores is located in the OpenHW Group's CORE-V documentation repo. Reading the Verification Strategy is strongly recommended.

If you want to run a simulation there are two options:

1. To run the CORE testbench (based on the RI5CY testbench), go to cv32/sim/core and read the README.
2. To run the CV32E40P UVM environment, go to cv32/sim/uvmt_cv32 and read the README.

Explainer for the CI flow used by CORE-V-VERIF.

Empty sub-directory into which the RTL from one or more of the CORE-V-CORES repositories is cloned.

Verification Environments, testbenches, testcases and simulation Makefiles for the CV32E cores.

Verification Environments, testbenches, testcases and simulation Makefiles for the CV64A cores.

Empty. Please see the CORE-V-DOCS repository.

Common components for the CV32 and CV64 verification environments.

We highly appreciate community contributions. You can get a sense of our current needs by reviewing the GitHub projects associated with this repository. Individual work-items within a project are defined as issues with a task label.

To ease our work of reviewing your contributions, please:

• Review CONTRIBUTING.
• Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
• Write meaningful commit messages.
• If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.