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GRMON2 unable to connect
It looks like I've been able to successfully do both make load-ram & make load-flash, but in either case I'm failing to connect to the miniSpartan6+ with grmon. I was hoping maybe you might be able to point out the error in my ways (I'm just starting out with this FPGA). I'm using Ubuntu 16.04 and have checked out the lastest copy of your repository. I have also tried the following with sudo as well.
Any assistance would be greatly appreciated, thank you!
leon3-mini-spartan6p master $ make load-flash
ngdbuild leon3mp.ngc -aul -uc ../../boards/mini-spartan6p/default.ucf -p XC6SLX25-ftg256-3 -sd ../../netlists/xilinx/Spartan3
Release 14.7 - ngdbuild P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild
leon3mp.ngc -aul -uc ../../boards/mini-spartan6p/default.ucf -p
XC6SLX25-ftg256-3 -sd ../../netlists/xilinx/Spartan3
Reading NGO file "/home/tad/Leon/grlib/designs/leon3-mini-spartan6p/leon3mp.ngc"
...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file
"../../boards/mini-spartan6p/default.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
INFO:ConstraintSystem - The Period constraint <NET "CLK50" PERIOD = 20 ns |>
[../../boards/mini-spartan6p/default.ucf(2)], is specified using the Net
Period method which is not recommended. Please use the Timespec PERIOD
method.
WARNING:ConstraintSystem - The Offset constraint <TIMEGRP "dram_in" OFFSET = IN
3 ns BEFORE "CLK50" RISING;> [../../boards/mini-spartan6p/default.ucf(133)],
is specified without a duration. This will result in a lack of hold time
checks in timing reports. If hold time checks are desired a duration value
should be specified following the 'VALID' keyword.
Done...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 1
Writing NGD file "leon3mp.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "leon3mp.bld"...
NGDBUILD done.
map -pr b -w -ol high -p XC6SLX25-ftg256-3 leon3mp
Release 14.7 - Map P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Using target part "6slx25ftg256-3".
Mapping design into LUTs...
Writing file leon3mp.ngm...
Running directed packing...
WARNING:Pack:1186 - One or more I/O components have conflicting property values.
For each occurrence, the system will use the property value attached to the
pad. Otherwise, the system will use the first property value read. To view
each occurrence, create a detailed map report (run map using the -detail
option).
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 10 secs
Total CPU time at the beginning of Placer: 10 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:245e656c) REAL time: 11 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:245e656c) REAL time: 11 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:245e656c) REAL time: 11 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:89fc089c) REAL time: 17 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:89fc089c) REAL time: 17 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:89fc089c) REAL time: 17 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:89fc089c) REAL time: 17 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:89fc089c) REAL time: 17 secs
Phase 9.8 Global Placement
.............................
...............................................................................
.........................................................................................
...................................................................................................................
.................................................
Phase 9.8 Global Placement (Checksum:6ef9f3ca) REAL time: 52 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:6ef9f3ca) REAL time: 53 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:e8d7c6d7) REAL time: 59 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:e8d7c6d7) REAL time: 1 mins
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:2d841d56) REAL time: 1 mins
Total REAL time to Placer completion: 1 mins 3 secs
Total CPU time to Placer completion: 1 mins 3 secs
Running post-placement packing...
Writing output files...
Design Summary:
Number of errors: 0
Number of warnings: 1
Slice Logic Utilization:
Number of Slice Registers: 2,233 out of 30,064 7%
Number used as Flip Flops: 2,233
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,041 out of 15,032 33%
Number used as logic: 5,013 out of 15,032 33%
Number using O6 output only: 4,229
Number using O5 output only: 63
Number using O5 and O6: 721
Number used as ROM: 0
Number used as Memory: 10 out of 3,664 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 10
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 8
Number used exclusively as route-thrus: 18
Number with same-slice register load: 14
Number with same-slice carry load: 4
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,690 out of 3,758 44%
Number of MUXCYs used: 376 out of 7,516 5%
Number of LUT Flip Flop pairs used: 5,332
Number with an unused Flip Flop: 3,207 out of 5,332 60%
Number with an unused LUT: 291 out of 5,332 5%
Number of fully used LUT-FF pairs: 1,834 out of 5,332 34%
Number of unique control sets: 153
Number of slice register sites lost
to control set restrictions: 733 out of 30,064 2%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 54 out of 186 29%
Number of LOCed IOBs: 54 out of 54 100%
IOB Flip Flops: 64
Specific Feature Utilization:
Number of RAMB16BWERs: 12 out of 52 23%
Number of RAMB8BWERs: 0 out of 104 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 1 out of 16 6%
Number used as BUFGs: 1
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 9 out of 272 3%
Number used as ILOGIC2s: 9
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 272 0%
Number of OLOGIC2/OSERDES2s: 47 out of 272 17%
Number used as OLOGIC2s: 47
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 160 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 1 out of 38 2%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.35
Peak Memory Usage: 815 MB
Total REAL time to MAP completion: 1 mins 6 secs
Total CPU time to MAP completion: 1 mins 6 secs
Mapping completed.
See MAP report file "leon3mp.mrp" for details.
par -ol high -w leon3mp leon3mp.ncd
Release 14.7 - par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Constraints file: leon3mp.pcf.
Loading device for application Rf_Device from file '6slx25.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
"leon3mp" is an NCD, version 3.2, device xc6slx25, package ftg256, speed -3
WARNING:ConstraintSystem - The Offset constraint <TIMEGRP "dram_in" OFFSET = IN 3 ns BEFORE COMP "CLK50" "RISING";>
[leon3mp.pcf(83)], is specified without a duration. This will result in a lack of hold time checks in timing
reports. If hold time checks are desired a duration value should be specified following the 'VALID' keyword.
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 2,233 out of 30,064 7%
Number used as Flip Flops: 2,233
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,041 out of 15,032 33%
Number used as logic: 5,013 out of 15,032 33%
Number using O6 output only: 4,229
Number using O5 output only: 63
Number using O5 and O6: 721
Number used as ROM: 0
Number used as Memory: 10 out of 3,664 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 10
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 8
Number used exclusively as route-thrus: 18
Number with same-slice register load: 14
Number with same-slice carry load: 4
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,690 out of 3,758 44%
Number of MUXCYs used: 376 out of 7,516 5%
Number of LUT Flip Flop pairs used: 5,332
Number with an unused Flip Flop: 3,207 out of 5,332 60%
Number with an unused LUT: 291 out of 5,332 5%
Number of fully used LUT-FF pairs: 1,834 out of 5,332 34%
Number of slice register sites lost
to control set restrictions: 0 out of 30,064 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 54 out of 186 29%
Number of LOCed IOBs: 54 out of 54 100%
IOB Flip Flops: 64
Specific Feature Utilization:
Number of RAMB16BWERs: 12 out of 52 23%
Number of RAMB8BWERs: 0 out of 104 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 1 out of 16 6%
Number used as BUFGs: 1
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 9 out of 272 3%
Number used as ILOGIC2s: 9
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 272 0%
Number of OLOGIC2/OSERDES2s: 47 out of 272 17%
Number used as OLOGIC2s: 47
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 160 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 1 out of 38 2%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 5 secs
Finished initial Timing Analysis. REAL time: 5 secs
WARNING:Par:288 - The signal SW(2)_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal SW(3)_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal SW(4)_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 30935 unrouted; REAL time: 6 secs
Phase 2 : 28750 unrouted; REAL time: 7 secs
Phase 3 : 15320 unrouted; REAL time: 18 secs
Phase 4 : 15320 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 19 secs
Updating file: leon3mp.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 33 secs
Total REAL time to Router completion: 33 secs
Total CPU time to Router completion: 35 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clkm_BUFG | BUFGMUX_X2Y11| No | 1014 | 0.695 | 1.738 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TIMEGRP "dram_in" OFFSET = IN 3 ns BEFORE | SETUP | 0.041ns| 2.959ns| 0| 0
COMP "CLK50" "RISING" | | | | |
----------------------------------------------------------------------------------------------------------
TIMEGRP "dram_out" OFFSET = OUT 12 ns AFT | MAXDELAY | 0.264ns| 11.736ns| 0| 0
ER COMP "CLK50" | | | | |
----------------------------------------------------------------------------------------------------------
NET "clkm" PERIOD = 20 ns HIGH 50% | SETUP | 4.404ns| 15.596ns| 0| 0
| HOLD | 0.390ns| | 0| 0
----------------------------------------------------------------------------------------------------------
All constraints were met.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 3 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 35 secs
Total CPU time to PAR completion: 37 secs
Peak Memory Usage: 745 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 6
Number of info messages: 0
Writing design to file leon3mp.ncd
PAR done!
trce -v 5 leon3mp.ncd leon3mp.pcf
Release 14.7 - Trace (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx25.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/.
"leon3mp" is an NCD, version 3.2, device xc6slx25, package ftg256, speed -3
WARNING:ConstraintSystem - The Offset constraint <TIMEGRP "dram_in" OFFSET = IN
3 ns BEFORE COMP "CLK50" "RISING";> [leon3mp.pcf(83)], is specified without a
duration. This will result in a lack of hold time checks in timing reports.
If hold time checks are desired a duration value should be specified
following the 'VALID' keyword.
--------------------------------------------------------------------------------
Release 14.7 Trace (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -v 5 leon3mp.ncd
leon3mp.pcf
Design file: leon3mp.ncd
Physical constraint file: leon3mp.pcf
Device,speed: xc6slx25,-3 (PRODUCTION 1.23 2013-10-13)
Report level: verbose report, limited to 5 items per constraint
--------------------------------------------------------------------------------
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in
the unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of
this model, and for more information on accounting for different loading conditions, please see the device datasheet.
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 1276897 paths, 0 nets, and 29765 connections
Design statistics:
Minimum period: 15.596ns (Maximum frequency: 64.119MHz)
Minimum input required time before clock: 2.959ns
Minimum output required time after clock: 11.736ns
Analysis completed Mon Feb 13 19:45:19 2017
--------------------------------------------------------------------------------
Generating Report ...
Number of warnings: 1
Number of info messages: 3
Total time: 8 secs
bitgen leon3mp -d -m -w -f ../../boards/mini-spartan6p/default.ut
Release 14.7 - Bitgen P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx25.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/.
"leon3mp" is an NCD, version 3.2, device xc6slx25, package ftg256, speed -3
Opened constraints file leon3mp.pcf.
Mon Feb 13 19:45:23 2017
Creating bit map...
Saving bit stream in "leon3mp.bit".
Saving bit stream in "leon3mp.rbt".
Saving Readback bit file leon3mp.rbb.
Saving Readback bit file leon3mp.rba.
Saving Readback golden data file leon3mp.rbd.
Saving mask data in "leon3mp.msd".
Creating bit mask...
Saving mask bit stream in "leon3mp.msk".
Bitstream generation is complete.
sudo xc3sprog -c ftdi -p0 ../../boards/mini-spartan6p/bscan_spi_s6lx25_ftg256.bit
XC3SPROG (c) 2004-2011 xc3sprog project $Rev: 785 $ OS: Linux
Free software: If you contribute nothing, expect nothing!
Feedback on success/failure/enhancement requests:
http://sourceforge.net/mail/?group_id=170565
Check Sourceforge for updates:
http://sourceforge.net/projects/xc3sprog/develop
Using Libftdi,
DNA is 0xf9ebb1c416a1f5fe
sudo xc3sprog -c ftdi -I leon3mp.bit
XC3SPROG (c) 2004-2011 xc3sprog project $Rev: 785 $ OS: Linux
Free software: If you contribute nothing, expect nothing!
Feedback on success/failure/enhancement requests:
http://sourceforge.net/mail/?group_id=170565
Check Sourceforge for updates:
http://sourceforge.net/projects/xc3sprog/develop
Using Libftdi,
JEDEC: c2 20 0x17 0xc2
Found Macronix MX25L Device, Device ID 0x2017
256 bytes/page, 262144 pages = 67108864 bytes total
Verify: Success!
leon3-mini-spartan6p master $ ls -l /dev/ttyUSB1
crw-rw---- 1 root dialout 188, 1 Feb 13 19:33 /dev/ttyUSB1
leon3-mini-spartan6p master $ groups
tad adm dialout cdrom sudo dip video plugdev input lpadmin sambashare wireshark
leon3-mini-spartan6p master $ /opt/grmon-eval-2.0.82/linux64/bin/grmon -uart /dev/ttyUSB1
GRMON2 LEON debug monitor v2.0.82 64-bit eval version
Copyright (C) 2017 Cobham Gaisler - All rights reserved.
For latest updates, go to http://www.gaisler.com/
Comments or bug-reports to [email protected]
This eval version will expire on 08/08/2017
using port /dev/ttyUSB1 @ 115200 baud
UART initialization failure, retrying
UART initialization failure, retrying
UART initialization failure, retrying
UART initialization failure, retrying
UART initialization failure, retrying
UART initialization failure, retrying
UART initialization failure, retrying
UART initialization failure, retrying
UART initialization failure, retrying
UART initialization failure, retrying
Exiting GRMON
UART failed to connect
grmon unble to connect digilent basys3
Hi,
I have synthesized my design for Basys3 digilent board. I used the design "leon3-digilent-basys3", the design got synthesized correctly and the bitfile is generated. I have problems in connecting to the design through grmon. I am getting the following error.
grmon-eval-3.0.7/linux/bin64> ./grmon -digilent -uart /dev/ttyUSB1
GRMON LEON debug monitor v3.0.7 64-bit eval version
Copyright (C) 2018 Cobham Gaisler - All rights reserved.
For latest updates, go to http://www.gaisler.com/
Comments or bug-reports to [email protected]
This eval version will expire on 25/11/2018
using port /dev/ttyUSB1 @ 115200 baud
UART initialization failure, retrying
UART initialization failure, retrying
UART initialization failure, retrying
UART initialization failure, retrying
UART initialization failure, retrying
UART initialization failure, retrying
UART initialization failure, retrying
UART initialization failure, retrying
UART initialization failure, retrying
UART initialization failure, retrying
ERROR! UART failed to connect
My SW(0) is "1" so that Debug UART is connected. Any hints on how to debug this issue?
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