ram.v for ice40UP5k about swapforth HOT 4 CLOSED

Hmm, am having trouble looking up the ice40UP5 - do you have a link?

from swapforth.

http://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40Ultra.aspx
ice40UP5k - Ultra Plus 5k - at the right hand side of the selection guide table

from swapforth.

Correct, the RAM contents should be possible.

With the correct J1a implementation in Verilog (including the UART pins hooked up) this should have a full set of words. It is a 4Kx16 RAM, contents in hex:
nuc.hex.txt

Then you will want to replace this file:

https://github.com/jamesbowman/swapforth/blob/master/j1a/icestorm/j1a.v

with a version for IceCube2. Keep the j1, the UART, and hook up the RAM initialized with the above file.
The IO ports won't apply to your board, so delete all that.

Hope this helps, J.

from swapforth.

Would it not be easier to have the "ram.v" source available (no need to run mkrom.py and gforth then)? You still need it in order to compile the j1a in Icecube2, afaik:
j1.v + j1a.v + ram.v + uart.v + stack2.v

from swapforth.