Related Issues (20)
- #flash and mkrom.py issue
- Fix for uart.v
- nandland.com go board HOT 7
- What's EASE_IO_TIMING for? HOT 3
- "$10 $0004 io!" does not turn the led on
- Initial port of j1b to Lattice ECP5 FPGA
- Incorrect literal with base-switching prefix changes the base for numerical conversions.
- Compilation of J1B with Verilator does not work in Linux/Debian. Small modification of j1b.v needed.
- Python Emulator Issues
- Completed port to TinyFPGA-BX board complete with soft USB port. HOT 1
- Can it use the irda ? HOT 1
- J1B does not compile with the newest Verilator 4.210 2021-07-07 rev v4.210-19-gde408a5e HOT 1
- [Feature request] further documentation on the J1 core versions HOT 2
- Strings on j1b
- The localtest doesn't work with Verilator 5.xxx HOT 3
- apio error, can find ram.v for j1a HOT 1
- Unnable to connect. HOT 6
- Converting j1a to use ICEbreaker HOT 4
- Data stack always empty HOT 1
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