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View Code? Open in Web Editor NEWVerilog behavioral description of various memories
License: MIT License
Verilog behavioral description of various memories
License: MIT License
testbench should write N words then check if w_level and r_level are N
replace "assim" with asym
replace "data_in/out" with "w/r_data"
verify the consistency of directory names, file names and module names
reg_file means sp_reg_file effect the change
what is the difference between the _big files and the one without this suffix?
replace with w_wide_r_narrow and w_narrow_r_wide
each terminal directory should contain 2 files: x, x_tb.v
write a top Makefile that simulates any memory module with icarus and opens gtkwave in background
make PATH=path/to/module/dir
etc
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