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Add FPGA build scripts for IC Bench FPGA board

Current procedure to uploading firmware to SoC:

1. Pull fetch_en to low; pull rst low
2. Pull rst high to make sure fetch_en low is sampled by SoC at boot time, and cpu core is halted
3. Upload firmware to SoC
4. Pull fetch_en high

To pull fetch_en low on a board, a switch or a jumper is required, and it is not convenient.

It is best to halt cpu core by writing to dbg registers:

1. For zeroriscy: write to DBG_CTRL
   zero-riscy: User Manual
2. For ri5cy: write to DCSR
   RI5CY User Manual

The expected uploading firmware procedure:

1. fetch_en is always high
2. SoC boot from boot ROM
3. Halt cpu core by writing to dbg registers
4. Upload firmware
5. Set next pc to reset_handler and start cpu core

Currently, testbench supports MEMLOAD in (PRELOAD, SPI, STANDALONE).

JTAG firmware download has been validated, and should be add to testbench.

And README should be updated after JTAG support.

sign named avalid_o is unused in RTL

axi_reg_word_rd.sv :
line 49 : output logic avalid_o ,
line 80 : assign avalid_o = s_ar_store;

axi_up_if.sv :
line 90 : .avalid_o (),

Current status:

1. FPGA build is based on original pulpino structure, and does not work on the current structure.
2. To adapt to various processes, some process related RTL sources under rtl/components have been moved to rtl/components/functional
3. PULP_FPGA_EMUL macro is used by RTL under rtl/components/functional
4. PULP_FPGA_EMUL macro is also used by other SoC RTL and IPs

Actions:

1. Consider fpga as a process, and make rtl/components/fpga directory
2. Put fpga specific RTL under rtl/components/fpga, and no PULP_FPGA_EMUL is required in that dir
3. Make rtl/components/functional RTL pure functional by removing FPGA related RTL
4. Modify FPGA build script to use fpga components RTL