hysum-tobbetu / aes-encryption-verilog-pipelined-implementation-128bit Goto Github PK

Device: Zedboard xc7z020clg484-1, Clock Rate: 319 MHz, Tool: Vivado 2018.3, Language: Verilog

Home Page: https://hysum-tobbetu.github.io/AES-Encyrption-Verilog-Pipelined-Implementation-128bit/

Pascal 0.01% Verilog 65.59% VHDL 6.79% SystemVerilog 1.07% V 2.87% Shell 0.25% Stata 0.02% Forth 0.01% Tcl 0.22% JavaScript 0.12% Batchfile 0.04% C 22.87% HTML 0.06% PureBasic 0.01% Coq 0.08%

aes-engine aes-wrapper clock-rate fpga matrix mds rcon-matrices sbox verilog vivado xor zedboard

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