Hello!

I found this repository from https://www.youtube.com/@LearnRISCV

Could you please add information about the license of this repository — is it allowed to copy, change and use the code in any purpose?
It would be great to see any popular open source license.

Hello

I am looking at "slide" "Sample PMP configuration (from E51 manual)"

Now the RAM region physical address is from 0x2000_0000 to 0x2000_8000 (32 KBytes). Presumably for RV32, the Physical address is 34-bits (33:0).

Now since pmpaddrx can only hold physical address bits [33:2], we then need to right shift the above address right by two bits.

This now gives the range as 0x0800_0000 to 0x0800_2000. Since the lower address bits in pmpaddrx encode the range, then to encode a range of 32KBytes, the value that needs to be programmed in the pmpaddrx is 0x0800_1fff.

However, the "slide" shows the pmpaddrx value to be 0x0800_0fff.

What am i missing?

Regards
JO

Hi, I am working on verifying access modes for RISCV CSRs, I am trying to verify Machine Mode Read only CSRs in lower privileged mode i.e on Supervisor Mode.

As per RISCV privileged Specification if we try to access Machine mode CSRs in lower privileged modes it will raise exception.

When i tried back-to-back read on MIMPID CSR in supervisor Mode it is expexted to raise exception for all access in supervisor mode but in my case it raises exception for first CSRR instruction for second and last CSRR instruction it didn't raised exception.
could anyone please help me in resolving this issue.

please find the test code here and let me know if any info needed.

Thanks

Hi I have seen your video I like to run gpio21on-off but i cannot see where it is , can you help me out to find it

I am really interested with this project as I am really new to RISC-V and trying to learn how to implement my own bootloader. May I know is there any step by step or guidance on how to use the boot program that you have developed in boards/hifive1-revb/src/start.s into QEMU? Because currently I did not purchase the board yet, however I am eager to learn how to run the code and simulate it using QEMU. I know there is a port for this board, which is sifive_e.

I really appreciate it if you can give some guidance on where to start working on this.

Hi !

I try to switch privilege mode between Machine-mode and User-mode on the CPU VexRiscv with variant Secure, Linux, Full. I created a SoC with the LiteX tools. I follow your video tutorial. I realized that here :

`

    uint32_t mstatus;
uint32_t mepc;
uint32_t user_entry;
__asm__ volatile ("csrr %0, mstatus" : "=r" (mstatus));
__asm__ volatile ("li t0, 0x8"); // set MIE bit
__asm__ volatile ("csrs mstatus, 0x8");
__asm__ volatile ("csrr %0, mepc" : "=r" (mepc));
__asm__ volatile ("lw %0, %1" : "=r" (user_entry) : "m" (*enter_user_mode));
__asm__ volatile ("csrw mepc, %0" : : "r" (user_entry));
__asm__ volatile ("csrr t0, mstatus");
__asm__ volatile ("li t1, 0xFFFFFFF8"); // set MPP to user mode
__asm__ volatile ("and t0, t0, t1"); // clear MPP bits
__asm__ volatile ("csrw mstatus, t0");
__asm__ volatile ("mret");

`

But, i get this result in the register mstatus, i read with GDB :

mstatus 0x1888 SD:0 VM:00 MXR:0 PUM:0 MPRV:0 XS:0 FS:0 MPP:3 HPP:0 SPP:0 MPIE:1 HPIE:0 SPIE:0 UPIE:0 MIE:1 HIE:0 SIE:0 UIE:0

I have the register mcause to 0x11 or 0x2 but my program gets stuck on the mret instruction.