hmdgharb / 5-staged-mips-pipeline Goto Github PK
View Code? Open in Web Editor NEWthis software is part of main project in Computer Architecture Laboratory which has been held in University of Tehran. for developing this project, i have used verilog Language in modelsim software. this project has been constructed, according to 5 staged MIPS pipeline (i.e. DesignSheet.jpg which included in the Design folder). the instruction set length of this project is 16 bit. the ALU of this Mips pipeline can do operation in Instruction Set of Type: R-Type Instruction set(register type: NOP, ADD, SUB, AND, OR, XOR, SL, SR, SRU, MUL) and I-Type Instruction set(Imediate Type: ADDI, LD, ST, BZ, JMP).
License: GNU General Public License v2.0