Program 1:

-> Basic gates using Data Flow Modelling

Program 2:

-> Half Adder using Behavioural (BM)

-> Half Adder using Data Flow (DFM)

-> Half Adder Structural Modelling (SM)

Program 3:

-> Full Adder using Data Flow Modelling

-> Full Adder using Data Flow and behavioural Modelling

-> Full Adder using Data Flow + Structural + Behavioural Modelling

-> 4 bit parallel adder using structural Modelling

Program 4:

-> 2x4 or 3x8 decoder using DFM

-> BCD to Decimal Decoder

-> BCD to Seven Segment Display

Program 5:

-> To realise and simulate Comparator

-> To realise and simulate Parity checker

-> To realise and simulate Parity generator

Program 6:

-> Design a SR flip flop

-> Design a JK flip flop

-> Design a T flip flop

Program 7:

-> D flip flop with synchronous reset

-> D flip flop with asynchronous reset

Program 8:

-> Serial adder using Structural modelling

-> Serial adder using Behavioural modelling

Program 9:

-> D - Latch simulation

-> SR - Latch using NOR gate

-> SR - Latch using NAND gate

Program 10:

-> MUX using Behavioural Modeling (BM)

-> MUX using Data Flow Modeling (DFM)

-> MUX using Data Flow Modeling with selected signal assignment(DFM)

Program 11:

-> 4-bit asynchronous counter using generate statement

-> 4-bit serial in parallel out shift register

-> 4-bit updown counter