Comments (8)
@gatecat
Can you add gf180mcu_fd_sc_mcu7t5v0_mux2_1
into no_synth.cells
and drc_exclude.cells
and try?
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PTAL - @atorkmabrains / @mkkassem
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This is obviously related to #2
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@RTimothyEdwards Could you check that?
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@atorkmabrains : I don't have a rule in magic that exactly implements the GF CO.6 rule. I would have to work out a much more complicated implementation of the rule. The rule is not exactly "overlap >= 0.06um in one direction" but is actually "overlap >= 0.06um in one direction if overlap < 0.04 in the other direction". There should be a way to implement this rule but I'll have to give it some thought. The klayout DRC deck should indicate that it's clean.
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@gatecat I advise that you run this design klayout DRC and see if it's violating.
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@RTimothyEdwards Thanks for indicating this.
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@gatecat I'll close this issue as there is no further communications. Please re-open if you still need any thing.
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Related Issues (16)
- Get the foss-eda-tools.googlesource.com mirror happening HOT 1
- Figure out how to fix the buffers schematic rendering
- Figure out how to fix the flip flop schematic rendering
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- Set up readthedocs pull request rendering HOT 1
- Miss-match in metal layer names between cells lef and tech lef
- Missing SITE definition HOT 3
- Missing Resistance for vias in tech lef HOT 14
- CI should check that the standard cells pass the GF180MCU DRC rules
- Gate level verilog modules are horribly broken and unusable HOT 16
- .spice netlist is messed up due to label placement HOT 1
- liberty issues with yosys
- Add missing definition.json files for each standard cell
- Technology LEF files have incorrect CPERSQDIST HOT 15
- Add verilog test benches for each of the standard cells.
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