This repo is "NTHU Electronic System Level Design" course project.

• origin: fix the original code from systemc 2.0, guarantee it works in systemc 2.3 enviroment
• src: assignment 1 source code
• log: contain each of output log of module

A 10-page report about what you learned at the Accellera Taiwan Forum.

• Design 1: Half and Full Adders Implement a half-adder, then use two half-adders to implement a full adder. Then synthesize the full adder using Cadence CTOS.
• Design 2: Finite Impulse Response Digital Filter Implement a 16th-order discrete-time Finite Impulse Response (FIR) digital filter, in 50MHz clock. Then synthesize the filter using Cadence CTOS.