Big board, big FPGA, plenty of pins and PCB space.
DDR3 is great but some for some low-latency application SDRAM is still better.
Can you see if possible to add a 32-bit 64MB SDRAM on the next release :)?

Top (PT) IO pins cannot do differential input. Most likely would be best to move to a pair of pins in one of the DDR3 banks.

Workaround for now is to use the 12MHz single ended clock, this seems fine for a PLL input.

also, any plans to do SD 4.0 or 7.0?

Any details about the MIPI capabilities of this board? Would it need any additional external interfacing, is it a Soft IP core ? if so how many LUT's does it use ?

An ultimate board should IMhO maximize external memory. Since 2 GiB chips are only ~$13, qty 1, maybe you’d consider going to that?

Just a schematic fix needed. Doesn't affect functionality as swap can be fixed in pinout for now.

Hello @daveshah1

Nice board! But why do you use local libraries? Some symbols (ex. 93AA46B_OT in eco_memory) exist in upstream KiCAD repository (93AAxxB in Memory_EEPROM). What do you think about my help for creating KiCAD repository PRs for the rest of the symbols (and may be footprints) with some reworkings in reasonable cases? It would be a good idea to use symbols from the repository in rev.1.1, woudn't it?

Best regards,
Anton Lysak

The Vf of the red and green LEDs combined is just enough (slightly under 3.3V) for them to light dimly even with the middle tristated. Perhaps this should be dropped a bit with a Schottky in the supply to avoid this.

Features tested so far:

• FT2232H JTAG and UART
• FT2232H parallel mode
• USB powered
• 12V power circuitry and connector
• LEDs
• Buttons and DIP switches
• DDR3 (tested up to 400Mbps at present)
• Ethernet PHY
• TFP410 HDMI (tested up to 1080p30 at present)
• USB ULPI PHY
• Clock generator
• PCIe
• M.2
• FFCs
• PMOD
• micro SD