Read FPGA bram content and transfer data to PC through Uart.
Summer research project at VLSI Design Institute, Yuquan Campus, Zhejiang University.
This is part of the work for PUF design. Mainly focused SRAM based PUFs.
Data Transfer COM: Uart
Baud Rate 9600
Parity Bit Even
Stop Bit 1
Data Length 8
FPGA: Xilinx VC707 Virtex-7 xc7vx485tffg1761-2
( PangoMicro Titan-2 based implementation is under development )
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