Summer Research Project at VLSI Design Institute, Yuquan Campus, Zhejiang University.
Instructor: Prof. Huang Kejie @ZJU
Special thanks to my seniors Wang Chengxuan & Yang Zhiyao.

This is a FPGA Implementation of Collision based SRAM PUFs. Read Write Collision (RWC) PUF would base on the literature A new read–write collision-based SRAM PUF implemented on Xilinx FPGAs.

UART implementation based on (verilog)UART协议详讲与实现. (NOT used yet, will replace ILA later)

Xilinx VC707 | Virtex-7 XC7VX485TFFG1761-2

• Baud Rate: 9600
• Parity Bit: Even
• Stop Bit: 1
• Data Length: 8

• Clock
  • Input: 200MHZ Differential Clock (System Clock)
  • Output: 350MHZ Single Port Clock
• Block RAM Generator
  • True Dual Port Mode (TDP)
  • Data Width: 32
  • Data Depth: 1024
  • Read & Write Delay: 1 cycle (No primitive register enabled)

Latest Progress is recorded in RTL Source Log, which is the README file in srcs folder.

• Read-Write Collision PUF
  • Single Port: FAILED
  • Dual Port: In progress, SUCCEED
• Dual-Port Write Collision PUF