Comments (2)
Yes this is a known problem. Do you happen to know what the equivalent mechanism to HWCAP
is on BSD?
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I'm slowly becoming more knowledgeable about aarch64 machines...
It seems Linux user-mode runs at EL1 allowing access to CPU feature registers like MIDR or ID_AA64PFR0_EL1 to succeed.
OpenBSD (at least) runs at EL0 therefore these instructions fail with SIGILL (illegal instruction).
I see two paths forward: grep the dmesg output for indicators; OpenBSD for now does not publish the full CPU feature set in the dmesg output for aarch64 (it does so for most other architectures.)
Or run test code, trap SIGILL and revert to "generic" if needed.
Both look about as hacky as can be imagined.
(I don't know what Apple machines do.) I'm testing on Raspberry Pi 4B.
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Related Issues (20)
- Discrepancy in Haswell Results for Dgemm HOT 5
- cspan: Suggesting an ergonomic C99 API with multidimensional matrices for BLIS HOT 10
- "Missing" symbols relative to OpenBLAS HOT 16
- triggers segfault in "make check" process with configuration --disable-sba-pools on CentOS (SkylakeX)
- Default BLIS_[MNK]T values never actually set HOT 9
- fatal error: malloc.h: No such file or directory HOT 2
- Header path for default source build and Debian should match HOT 6
- bli_gemmsup_rd_haswell_asm_d6x8m.c:1296:1:error:bp cannot be used in ams here HOT 3
- New release? HOT 6
- A more complete list of ARM cpu implementations
- inconsistence between documentation and code for bli_?trmm3 HOT 5
- What is the best way to debug BLIS? HOT 2
- GPU support and PortBLAS HOT 4
- getting error as illegal instruction HOT 4
- Support compiler names with spaces HOT 1
- Regarding Default Behaviour for CPU Affinity HOT 4
- BF16 on AMD CPU? HOT 4
- Upstream BLIS patches for ARM SVE? HOT 5
- Memory location in the prefetch instructions HOT 5
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