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Probably not needed, replace with simple TVS diodes. Design in conjunction with #6

Implement real MEAS commands that start a new measurement.

Test with powerfull fan: MR3010E with 12V with PWM (datasheet).

Disadvantage: expensive and only available from Digikey. It really has to make a difference.

using protocol developed in V7.

Wire IEXT document for stand alone version.

Run test with both transformers and remove T1 or T2 footprint in final version depending on choice.

T2 is working but less power efficient and expensive.
T1 still needs to be tested.

Long term which. Main problem is to find space for the additional hardware on the main PCB.

3 available DAC channels can be used to set the levels/slew rates

We need to find a good placement of the 4 MOSFETS on the LAM 3 150 heat sink. The MOSFETs are fixed on the PCB and it would require a special setup to move them around or a lot of different PCB’s to test different configurations.

A form of thermal analysis simulation to find an optimal/good placement seems more feasible. The analysis is not very trivial because the fan cases a forced airflow thru the heatsink and the air will heat up while flowing thru the heatsink.

On my current test PCB the MOSFETS are evenly placed along the heatsink and all MOSFETS dissipate the same amount of power (this is forced by the circuit). This situation results in the MOSFETS further away from the fan being around 15-20 degrees Celsius higher. The maximum temperature of the individual MOSFETs places the limit on the maximum power rating of the device. In my test I can now dissipate 90W total in a 19 degrees room temperature. The heatsink close to the MOSFET with highest temperature is just below 90 degrees Celsius.

The MOSFETS are IRF250 in TO-247 package with thermal grease and a kapton foil isolation. They are pressed against the heatsink with DIY clamps at the place of the screw hole of the package. Because of the experimentation I don’t want to drill a lot of holes in the heatsink.

Thermal images show a gradual increase in heatsink temperature when moving away from the fan. The increase is comparable to the temperature difference between the MOSFETS. Therefore I think it is worth investigating if placing all the MOSFETS closer to the fan results in a possible lower maximum MOSFET temperature at the same overall power dissipation.

A good/optimal placement maximises the total power the mosfets can dissipate without individually overheating.
For this I think there are 2 degreees of freedom we should focus on:

1. placement of the 2 MOSFETS with the greatest distance from the fan. The other mosfets should be placed close to the fan.
2. Create a Fixed difference (in %) between currents (which is directly proportional to the power) of the MOSFETS close and far away of the fan. If simulation shows this is beneficial it is straight forward to create this fixed difference in the circuit.

I think we should first optimise on 1 and second on 2.

Evaluate the v3 hardware implementation. Is it useful, e.g. does it give extra measurement accuracy or not.

Check if implementation this adheres to original separate tasks.

This should prepare for V7 firmware split.

The Analog V4 schematic and PCB have some changes that need testing after fabrication:

• Test reverse polarity protection circuit
• Test reverse polarity with remote voltage sensing voltage enabled.
• Test -1V reference
• Test dynamic behaviour of Von

• Add ESD protection to Sense inputs
• Add ESP protection to main power inputs. Is this necessary ?

Separated from #7:
For ease of testing also add an optional 12V to 5V buck converter to allow for a single 12V power supply for testing.

Add this to the isolated power section of the Power-MCU board. Should be optional using jumpers.

Errors found on r1r1:

• TFT Display connector is rotated 180 degrees.
• TFT Display connector is about 1mm misaligned with TFT display connector.
• Move MCP23008 up to keep it clear from MCU-Power PCB in case (or make cutout on MCU-Power PCB see #2 )
• Correct encoder footprint

Change power section to have a 5V input for the isolated power rails and separate 12V input for the fan connections and the fan controller (non isolated).

For ease of testing also add an optional 12V to 5V buck converter to allow for a single 12V power supply for testing.

This is a variation of the CR mode: It has a voltage offset before it starts conducting.

This can be implemented in firmware only. No hardware changes required

Rework the Power-MCU PCB to be a piggy board:

• Flip the board to fit on top of the BB3 board and connectors.
• Keep/Include Pico
• Keep MCP23017 section with level shifting
• Keep/include isolated power section (simplify?!)
• Keep heatsink fan controller
• Keep panel connector for display/touch/keys
• Keep Debug interface SWD+UART
• Add: DIB opto isolators
• Add: allow to switch between panel and DIB isolators (jumpers?)
• Remove case fan controller
• Remove 12V - 5V module/section
• Optionally/TBD: Add leds and extend piggy board to panel. Banana connectors and or sense relay might be in the way.

Implement self test function and add it to startup and *TST? command.

Due to hardware limitations a full functional test is not possible without additional circuitry but a few sanity check can be implemented:

• ADC should trigger measure task (not really needed because watchdog might catch this?)
• measure voltage, perform range switch. Voltage should be same within a certain spec.
• same for current.
• set OCP DAC to 0 and MAX and see if it triggers/clears
• same for OVP DAC
• Manual Fan test

The revision D (2022) of the MCP23017 states the GPA7 (and GPB7) pins are output only. Currently we use GPA7 for Von input and this is working fine but can’t be relied upon.

Solution: Change the hw pin for von to a different pin of bank A. Swap it with an output pin.

Create a PCB with:

• RP2040 CPU / use raspberry pi pico module
• Connector to panel PCB with display, touch, and encoders. Using existing connector setup.
• 12V -> 5V module to feed BB3 module with both 12V and 5V.
• Case fan controller and drivers.

This PCB can be derived from the MCU-Power PCB.

Evaluate the v3 hardware implementation. Is it useful, e.g. does it give extra measurement accuracy or not.

See #22

Current reverse polarity implementation is a very crude diode+fuse: Implement a proper reverse polarity circuit preferabbly with a detection to software (nice to have).

Split the firmware between 2 RP2040's and have them sync state via SPI.

Von circuitry causes some oscillation when the voltage slowly decreases to the set level. This is noticeable in a typical battery discharge test, but this scenario can be circumvented easily by the user with the current firmware.

As this ia a very valid and common scenario we should implement something for it in hardware or software to notify user or avoid it.

• C401 = 1u (was 680n)
• C52 10uF cap should have higher voltage rating (25/50V)
• C316 = 1uF ipv 2.2uF. Change in design?
• R330 label is at wrong/unclear place (to close to R322)
• LT1964 PCB is correct for fixed 5V regulator. (adjustable requires additional 1200+390 ohm resistors)
• Fix +12V regulator setup (values below result in 11,5 V which is fine):
• remove R39
• R40 = 200
• R41 = 1k8
• GCOM op differential amplifiers shunt resistors instead of GND: R213, R211, R233, R231: GND change to GCOM.
• R6 should be connected to GCOM instead of GND. This relates to previous item.
• R18 en R19 = 470 ohm instead of 100k.
• U10B -1V reference circuit doesn't work. Fix.
• Connect -5V to R320 (instead of -1V) and replace R320 with 47k. After this: tune the Von response time.
• R201, R221, R202, R222 can be removed.
• R203, R205, R223, R225 = 10k. This improves the set current stability when temperature rises.

On piggy board:

• Add USB-C connector with relevant power connectors
• Possibly: fixed pull-up/pull-down resistors
• FUSB302MPX
• Connector to analog board for the power channels
• ESD protection

On analog board:

• Add connectors for the power channels.

Also look at Spark Analyzer

Create a studio dashboard that creates MPPT specific graphs and calculates results.

The graphs will be:

• Current-Voltage
• Power-Voltage

#8 will put to much stress on the mosfet driving opamps with the current clamp circuit.

Change the clamp method by clamping LoopIset to zero instead of the MOSFET gates.
Use a 2N7002 + resistor (1k?) + diode (1N4148) to clamp LoopIset to zero or slightly below zero.

Remove the lamp MOSFETS and the long lines to it.

• This is a DIB module size
• the main communication connector is in place
• the EEPROM is placed on analog PCB
• there is a connector routing the SPI and power connections to a (to be designed) piggy board
• screw holes for panel are in place
• the DIB power channel connector for parallel /serial operation is not implemented and wouldn't fit: one of the banana sockets is in the way and there is not much place left to shift everything over. It is also not clear if this would be useful to have.

Check if the rise/fall times of the ovp,ocp and von comparators and other digital inputs are in the range of the used logic family/ic’s. If not they need to be replaced with Schmitt-trigger equivalents.

Von doesn't have to be possible for the full voltage ranges, 50% of the range is enough. This might increase the accuracy of Von.

This can be implemented using voltage dividers. This is already in place on v3 of PCB.

During changes to reduce temperature dependencies some instability was introduced to the CC loop for low voltages (2-7V) and and multiple amps (2-4A). The measured oscillation is around 65kHz (using 10kohm feedback resistors for R225,R223, R205, R203)

Spice simulation agrees with this.

New values:

• gate resistors R207, R208, R227, R228: 10ohm (was 100) did not help
• feedback restores R203, R205, R223, R225: 22k (was 100k in V3C)
• compensation caps C213, C214, C227, C228: 1n (was 470p)

There are some mistakes on 2r2:

• diodes on negative rails are reversed (D7 & D8)
• Enable pin (pin 5) on sn6505 is low instead of high
• remove C3 and D4. Short jumper JP1. Configuration with 2 diodes is enough.
• remove zener D16 or change to higher value (18-20V)
• Remove T1 or T2 footprint in final version depending on choice no in #24
• Fix T1 component label (footprint is ok)
• Add cutout for MCP23008 on panel PCB.
• J7 pin 14 = GND, should be 3.3VD (power supply for ADC and DAC's on analog board)
• Fix Q1 an Q2 footprints. SOT23-3 instead of SOT23?

Improvements:

• in test PCBs: Add led to +15VU. This wil work as a small dummy load when analog board is not connected.

Implement watchdog in firmware to asses if all threads are functioning properly.

Add testpoints to PCB for easier testing.

• Several GND pins close to other testpins (to avoid loops)
• +12V
• +5V
• -5V
• V Ref
• -2.5V
• +3.0V
• LoopISet
• Imon
• Umon
• Imon for each loop

When a range switch happens this not always results in the right calibration values being used for displayed value.
Noticed on voltages.
This also happens when leaving calibration mode (during setDefaults).

going back and forth solves the problem.