This Repository contains a Test Design for partially reconfiguring a Xilinx 7-Series FPGA via the ICAP Interface over UART from a PC. For using the DFX functionality of Xilinx FPGAs, it is recommended using Vivado Version greater than 2021.2. While this test design is applicable to any Xilinx 7 series FPGA, it was designed to run on the Digilent Nexys 4 DDR Board (Xilinx Artix-7 XC7A100T-1CSG324C).

The whole Setup is split up in three parts:

1. The Verilog Design running on the FPGA containing the UART Transceiver and ICAP Controller: icap_controller
2. The Python GUI for writing partial Bitstreams: icap_gui
   • The necessary Python Packages are listed in requirements.txt
3. The Test Bitstreams suitable for the Nexys 4 DDR: Bitstreams
   • The partial Bitstreams shift_left/shift_right are supplied in the .bit and .bin format
   • The Bitstream bridge_wrapper_full.bit in shift_left/shift_right configures the static as well as the reconfigurable portion of the Design

Detailed Information about the ICAP Interface as well as the Test Design and setting up DFX can be found in Chapter 2 and Appendix A1