Benmarks written in Chisel/Verilog/BTOR2/AIGER for circuit verification

Chisel and Verilog divider implementation.

• Restoring divider
• Nutshell fixed clock divider

• Non-opt non-restoring divider

  • high-level

  • low-level (loop flattened)

  • gate-level translated by yosys

    read_verilog filename.v
    synth -flatten
    clean -purge
    abc -fast -g simple,MUX
    write_verilog filename-gl.v
    

• Dividers from FMCAD'22 benchmark

  • gate-level opt-old/new non-restoring divider
  • gate-level restoring divider

Translated from Verilog by yosys

read_verilog filename.v
synth -flatten
clean -purge
aigmap (abc -fast -g AND)
write_aiger -ascii -symbols filename.aag