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Modular cycle-accurate NES emulator implemented from scratch

License: GNU General Public License v3.0

C++ 93.94% CMake 2.87% Starlark 0.87% Python 2.32%

emulator nes cpp hacktoberfest

n_e_s's Introduction

n e s

Description

Modular cycle-accurate NES emulator implemented from scratch in modern C++ and built with the help of modern CMake, or that's the goal at least. If all goes according to plan, you should be able to rip the 6502 CPU library out of this and make a C64 or Apple ][ or whatever emulator based on it.

Building

Clone!

git clone https://github.com/evilcorpltd/n_e_s.git

Build!

mkdir build_ && cd build_
cmake ..
make
make test

n_e_s's People

Contributors

Stargazers

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Forkers

mkiael johnor robinlinden 18645504000 sa12123 cjuub ricardicus

n_e_s's Issues

Set up test with nestest

We should set up an integration test running nestest (http://nickmass.com/images/nestest.nes) and verify it against correct output here: http://www.qmtpro.com/~nes/misc/nestest.log

See: https://wiki.nesdev.com/w/index.php/Emulator_tests

Implement missing addressing modes for STA

Missing:
9D Absolute,X
99 Absolute,Y
81 Indexed-indirect
91 Indirect-indexed

Add support for more mappers

Having support for mappers 0-5 is probably a good start.

LSR should clear N flag

It seems like the negative status flag should always be cleared when doing a LSR operation: https://www.c64-wiki.com/wiki/LSR

LSR affects 3 of the CPU's status flags:

The negative status flag is always unconditionally cleared.

The zero flag is cleared unless the operand is zero

The carry flag is copied from the least significant bit (bit 0) of the operand prior to shifting

We do not clear the negative status flag right now:

        case LSR_A:
            pipeline_.push([=]() {
                set_carry(registers_->a & 1);
                registers_->a &= ~1;
                registers_->a >>= 1;
                set_zero(registers_->a);
            });

Implement instruction SBC

https://www.c64-wiki.com/wiki/SBC

Implement instruction CMP

See https://www.c64-wiki.com/wiki/CMP

Refactor rom handling to easier to support different mappers

A lot of the functionality between mappers are similar. We should probably have a mapper interface that translates an address on the cpu or ppu bus to a new address, and let the rom memory be owned by a shared rom-object

Implement instruction DEC

https://www.c64-wiki.com/wiki/DEC

Implement instruction JSR

See https://www.c64-wiki.com/wiki/JSR

Add missing dummy reads/writes

A lot of the 6502 instructions write even when they have no reason to. We've skipped this in places. We should set up an integration test checking dummy reads/writes and add them as they can cause side-effects.

Look into replacing Appveyor w/ Azure devops

Azure devops supports multiple parallel jobs and unlimited build minutes for open source projects. Appveyor's VS2019 job has been broken for weeks and only supports 1 build at a time meaning our Appveyor CI is always what's blocking the longest.