This repository contains a SystemVerilog implementation of a RISC-V processor project. The main objective of this project is to provide a reliable and high-performance solution for executing RISC-V instructions.

The repository is structured as follows:

• design: Contains the source code of the RISC-V processor project.
• doc: Contains the report.
• sim: Contains the simulation files and its results.
• verif: Contains the testbench files.

• For additional information on the implementation, please refer to the report.pdf.
• To get started with the RISC-V instruction set, please refer to:
  • The RISC-V Instruction Set Manual Volume I: User-Level ISA - Document Version 2.2
  • The RISC-V Instruction Set Manual Volume I: Unprivileged ISA - Document Version 20191213
• To simulate and test the RISC-V processor project, please use the following software: ModelSim-Intel® FPGAs Standard Edition Software Version 20.1.1

The following table lists the implemented instructions and their status. The instructions are listed in the order they appear in the RISC-V ISA manual.

• joaopmarinho
• nathaliafab

We extend our appreciation to Yifan Xu for their project, which provided the groundwork for this repository.