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RISC-V soft-core PEs for TaPaSCo

Verilog 24.56% Tcl 38.61% Makefile 3.84% C 5.84% Assembly 1.34% CMake 0.16% Shell 2.10% C++ 12.57% Cap'n Proto 0.15% Rust 10.48% Python 0.36%

fpga risc-v

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kmeinhar mfkiwl tsmk94 sajjadtamimi 7fm vuduydidan quangtran2796 tomenendal markussha timksf jrmejiaa flmeisel

tapasco-riscv's Issues

Is `swerv_eh1` core deprecated?

Hi all,

The rule swerv_setup is no longer working with the core Cores-VeeR-EH1 (previous SweRV). I saw that there is a fork of this core with the rule swerv_eh2_setup. This means that the rule and work of swerv_setup and swerv_pe is deprecated?

Thank you,

Not compatible with Vivado 2019.2

Vivado 2019.2 does no longer allow create_bd_addr_seg on unconnected segments. All cores do this in their specific_tcl scripts. Move the part into separate functions to call later in the block design build process.

Name change in flute ports

Memory ports of flute have changed their naming. Probably affects Piccolo as well.

Allow loading of programs which are not a multiple size of 8 Bytes on Ultra96

Error Description

When loading a program (e.g. simple_sum) on ultra96, a Bus Error occurs if the program is not a multiple of 8 Bytes in size.

Expected Behaviour

A program of any size should load.

Current Behaviour

A Bus Error occurs:

[root@alarm bld]# ./simple_sum_host /home/alarm/simple_sum.bin 
Finished reading binary file. Received 16401 bytes.
Bus error (core dumped)

Workarounds

This can be fixed by introducing an 8-aligned section filled with 8 Bytes at the end of the linker file (but this is a dirty hack.

CVA5: m_axi_cache interface seems to be disconnected

Description

When using Ultra96, I am not able to write to the DRAM of the PS from a PE. The writes are supposed to exit CVA5 from the m_axi_cache AXI interface. This interface seems to not be connected to anything in the SystemVerilog wrapper shipped by TaPaSCo.

E.g. when looking at the main AXI interface (m_axi), it is connected to CVA5 in the wrapper (see lines 150-185 in cva5_wrapper.sv) but the second Interface (just called axi) seems to be left dangling.

Expected Behaviour

I should be able to access the DRAM of the PS.

Fix/extend clean target

Cores must be deleted from TAPASCO_WORK_DIR instead of TAPASCO_HOME. Git clones and other stuff is not cleaned properly as well.

Debugging: writes less than 4 bytes fail

Verbose log from OpenOCD:

Debug: 3454420 26428 riscv-013.c:2824 mem_should_skip_progbuf(): Skipping mem write via progbuf - insufficient progbuf size.
Debug: 3454421 26428 riscv-013.c:2864 mem_should_skip_sysbus(): Skipping mem write via system bus - unsupported size.
Debug: 3454422 26428 riscv-013.c:3006 write_memory_abstract(): writing 1 words of 2 bytes from 0xee0081f4
Debug: 3454423 26428 tapasco-axi-jtag.c:348 axi_jtag_execute_command(): axi_jtag_execute_command: cmd->type: 1

/* shortened */

Debug: 3454827 26429 tapasco-axi-jtag.c:252 axi_jtag_execute_scan(): DR scan type 3 62 bits; starts in RESET end in RUN/IDLE
Info : 3454828 26429 tapasco-axi-jtag.c:323 axi_jtag_execute_scan(): TAPASCO: DMI: op: 0, data: 0 addr: 16 tdo: c08
Debug: 3454829 26429 commands.c:265 jtag_read_buffer(): fields[0].in_value[41]: 0x000000000c08
Debug: 3454830 26429 core.c:966 default_interface_jtag_execute_queue(): JTAG DR SCAN to RUN/IDLE
Debug: 3454831 26429 core.c:973 default_interface_jtag_execute_queue():   41b out: 005800000000
Debug: 3454832 26429 core.c:978 default_interface_jtag_execute_queue():   41b  in: 000000000c08
Debug: 3454833 26429 riscv-013.c:402 scan(): 41b - 00000000 @16 -> + 00000302 @00; 0i
Debug: 3454834 26429 riscv-013.c:806 execute_abstract_command(): command 0x2110000 failed; abstractcs=0x302

Vexriscv fails read/write from main memory on PYNQ

Read/Writes via HP port to main memory seem to fail. But e. g. on the Ultra96 the same software and core configuration runs without problems.

Update PicoRV32 url

PicoRV32 apparently moved to YosysHQ. We need to update it.

CVA6 core failing to build

I'm trying to build the CVA6 core and generate the bitstream to load the PE onto an ZCU102 board. Unfortunately, the build process does not seem to terminate properly, and I'm faced with this error when I run make cva6_pe:

ERROR: [BD 41-1075] Cannot create master segment for slave segment </cva6_timer_0/axi_timer/reg0> in address space </cva6_0/io_axi_mem> at offset and range 0x1300_0000 [ 768K ]. Range = 0x000C_0000. Memory ranges must be a power of 2..
Exec Tcl: create_bd_segment -offset <0x13000000> -range <0x00000000000C0000> -slave_segment </cva6_timer_0/axi_timer/reg0> -parent_addr_space </cva6_0/io_axi_mem> -name <SEG_cva6_clint>
ERROR: [BD 5-14] Error: running create_bd_segment.
ERROR: [Common 17-39] 'create_bd_addr_seg' failed due to earlier errors.

    while executing
"create_bd_addr_seg -range $CLINT_LENGTH -offset $CLINT_BASE [get_bd_addr_spaces cva6_0/io_axi_mem] [get_bd_addr_segs cva6_timer_0/axi_timer/reg0] SEG_..."
    (procedure "create_specific_addr_segs" line 23)
    invoked from within
"create_specific_addr_segs"
    (file "common/common_addr_segments.tcl" line 46)

    while executing
"source common/common_addr_segments.tcl"
    (procedure "cr_bd_riscv_pe" line 57)
    invoked from within
"cr_bd_riscv_pe "" $lmem"
    (file "riscv_pe_project.tcl" line 159)
INFO: [Common 17-206] Exiting Vivado at Wed Oct  4 12:21:17 2023...
make: *** [Makefile:29: cva6_pe] Error 1

Could I get some help with this? Also, as I understand it, once the PE is generated, it is also imported automatically into Tapasco. What are the next steps to generate and load the core onto the FPGA? Thanks!

How to run Dhrystone on a specific PE within TaPasCo?

Hello

I want to run some benchmarks on the PE's available within TaPasCo beginning with Dhrystone. I had a look on the makefile but it seems only related to the hardware generation and the boards. I did not find specific instructions to run benchmarks on FPGA.
The documentation link seems broken.
Could you point me to the documentation or the necessary steps to run Dhrystone?

Thank you

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