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OpenTitan: Open source silicon root of trust

Home Page: https://www.opentitan.org

License: Apache License 2.0

Makefile 0.06% C 19.72% SystemVerilog 45.70% Shell 0.44% C++ 5.27% Tcl 1.32% Stata 0.01% Python 8.34% HTML 0.37% Assembly 2.54% Dockerfile 0.03% CSS 0.14% Smarty 4.20% Emacs Lisp 1.90% Rust 5.98% SCSS 0.07% Verilog 0.03% Starlark 3.75% JavaScript 0.09% Handlebars 0.05%

opentitan's Introduction

About me

  • I'm currently working at Lowrisc as a Firmware engineer. Where I'm mostly colaborating to Opentitan (An open source silicon Root of trust).
  • I'm currently learning Rustlang and Embedded Rust.
  • I'm an enthusiast of RISC-V assembly.

opentitan's People

Contributors

a-will avatar alphan avatar andreaskurth avatar cfrantz avatar cindychip avatar ctopal avatar dmcardle avatar engdoreis avatar eunchan avatar gregac avatar hu90m avatar imphil avatar jadephilipoom avatar jdonjdon avatar jesultra avatar jwnrt avatar lenary avatar marnovandermaas avatar martin-lueker avatar matutem avatar mcy avatar milesdai avatar moidx avatar msfschaffner avatar mwbranstad avatar pamaury avatar rswarbrick avatar timothytrippel avatar vogelpi avatar weicaiyang avatar

opentitan's Issues

[chip-test, chip_aes] chip_sw_aes_prng_reseed

Test point name

chip_sw_aes_prng_reseed

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, spi_host] chip_sw_spi_host_configuration

Test point name

chip_sw_spi_host_configuration

Host side component

Rust?

Opentitantool infrastructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_aes] chip_sw_aes_enc

Test point name

chip_sw_aes_enc

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_aes] chip_sw_aes_force_prng_reseed

Test point name

chip_sw_aes_force_prng_reseed

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_adc_ctrl] chip_sw_adc_ctrl_oneshot

Test point name

chip_sw_adc_ctrl_oneshot

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_aes] chip_sw_aes_masking_off

Test point name

chip_sw_aes_masking_off

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_otp_ctrl] otp_ctrl_partition_access_locked

Test point name

otp_ctrl_partition_access_locked

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_aes] chip_sw_aes_sideload

Test point name

chip_sw_aes_sideload

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_otp_ctrl] otp_ctrl_check_timeout

Test point name

otp_ctrl_check_timeout

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_aes] chip_sw_aes_multi_block

Test point name

chip_sw_aes_multi_block

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_csrng] chip_sw_csrng_lc_hw_debug_en

Test point name

chip_sw_csrng_lc_hw_debug_en

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_csrng] chip_sw_csrng_fuse_en_sw_app_read

Test point name

chip_sw_csrng_fuse_en_sw_app_read

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_otp_ctrl] chip_sw_otp_ctrl_program_error

Test point name

chip_sw_otp_ctrl_program_error

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_adc_ctrl] chip_sw_adc_ctrl_debug_cable_irq

Test point name

chip_sw_adc_ctrl_debug_cable_irq

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, csrng] chip_sw_csrng_fuse_en_sw_app_read

Test point name

chip_sw_csrng_fuse_en_sw_app_read

Host side component

Rust?

Opentitantool infrastructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_otp_ctrl] chip_sw_otp_ctrl_escalation

Test point name

chip_sw_otp_ctrl_escalation

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_otp_ctrl] chip_otp_ctrl_init

Test point name

chip_otp_ctrl_init

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_csrng] chip_sw_csrng_edn_cmd

Test point name

chip_sw_csrng_edn_cmd

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_aes] chip_sw_aes_entropy

Test point name

chip_sw_aes_entropy

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, csrng] chip_sw_csrng_edn_cmd

Test point name

chip_sw_csrng_edn_cmd

Host side component

Rust?

Opentitantool infrastructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_otp_ctrl] chip_sw_otp_ctrl_lc_signals

Test point name

chip_sw_otp_ctrl_lc_signals

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_otp_ctrl] chip_sw_otp_ctrl_vendor_test_csr_access

Test point name

chip_sw_otp_ctrl_vendor_test_csr_access

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, spi_host] chip_sw_spi_host_events

Test point name

chip_sw_spi_host_events

Host side component

Rust?

Opentitantool infrastructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_otp_ctrl] chip_sw_otp_ctrl_keys

Test point name

chip_sw_otp_ctrl_keys

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_otp_ctrl] chip_sw_otp_prim_tl_access

Test point name

chip_sw_otp_prim_tl_access

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, spi_host] chip_sw_spi_host_pass_through

Test point name

chip_sw_spi_host_pass_through

Host side component

Rust?

Opentitantool infrastructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_gpio] chip_sw_gpio_in

Test point name

chip_sw_gpio_in

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_otp_ctrl] otp_ctrl_calibration

Test point name

otp_ctrl_calibration

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_otp_ctrl] chip_sw_otp_ctrl_hw_cfg0

Test point name

chip_sw_otp_ctrl_hw_cfg0

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_gpio] chip_sw_gpio_irq

Test point name

chip_sw_gpio_irq

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_aes] chip_sw_aes_idle

Test point name

chip_sw_aes_idle

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_gpio] chip_sw_gpio_out

Test point name

chip_sw_gpio_out

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_csrng] chip_sw_csrng_known_answer_tests

Test point name

chip_sw_csrng_known_answer_tests

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_adc_ctrl] chip_sw_adc_ctrl_normal

Test point name

chip_sw_adc_ctrl_normal

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_otp_ctrl] chip_sw_otp_ctrl_entropy

Test point name

chip_sw_otp_ctrl_entropy

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_aes] chip_sw_aes_interrupt_encryption

Test point name

chip_sw_aes_interrupt_encryption

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_adc_ctrl] chip_sw_adc_ctrl_sleep_debug_cable_wakeup

Test point name

chip_sw_adc_ctrl_sleep_debug_cable_wakeup

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

[chip-test, chip_otp_ctrl] chip_sw_otp_ctrl_program

Test point name

chip_sw_otp_ctrl_program

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

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