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"Compiler Optimisation Techniques" - BSc Computer Science Final Year Project (Sheffield Hallam University)

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arm armv7 c clang compiler optimization

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Allow project to build without tracy submodule

Tracy (the profiler) is definitely an optional dependency and the project should build & function without it, but currently cmake errors out if the tracy submodule is not present.

Create `MachineInsn` class that derives from `Instruction` - used to represent all machine instructions.

Test f5013-cconv-return-small-struct.c fail

struct MyStruct
{
  int a;
};

struct MyStruct get_small_struct()
{
  struct MyStruct a = { 33 };
  return a;
}

MyStruct = struct { i32 }

@ci0:ptr = global i32 0:i32
@ci1:ptr = global i32 33:i32

function get_small_struct(): void {
.0:
        stack_alloc [i8 x 4], %0:ptr
        stack_alloc [i8 x 4], %1:ptr
        ptrtoint [ptr -> i32], %1:ptr, %2:i32
        load @ci0:ptr, %3:i32
        iadd %2:i32, %3:i32, %4:i32
        inttoptr [i32 -> ptr], %4:i32, %5:ptr
        load @ci1:ptr, %6:i32
        store %6:i32, %5:ptr
        load %1:ptr, %7:MyStruct
        store %7:MyStruct, %0:ptr
        br .1
.1:
        load %0:ptr, r0:i32
        ret
}

[2022-02-14 03:02:17.238] [general] [info] Creating module from 'C:\helix\t.c'
[2022-02-14 03:02:17.240] [driver] [trace] End frontend compilation
[2022-02-14 03:02:17.240] [driver] [trace] Begin middle & backend compilation
[2022-02-14 03:02:17.241] [pass_manager] [trace] Registered pass (1) 'genlegal' - [Generic] Legalise illegal constructs IR to a legal equivilant
[2022-02-14 03:02:17.241] [pass_manager] [trace] Registered pass (2) 'structslegal' - [Generic] Legalise loading & storing struct types to/from virtual registers
[2022-02-14 03:02:17.241] [pass_manager] [trace] Registered pass (3) 'retcomb' - [Generic] Combine multiple returns into a singular exit point
[2022-02-14 03:02:17.241] [pass_manager] [trace] Registered pass (4) 'genlower' - [Generic] Lower high level IR constructs
[2022-02-14 03:02:17.241] [pass_manager] [trace] Registered pass (5) 'consthoist' - [ARM] Split and hoist constants to a form compatible with the ARM
[2022-02-14 03:02:17.241] [pass_manager] [trace] Registered pass (6) 'cconv' - [ARM] Lower IR to be compatible with the platform calling convention
[2022-02-14 03:02:17.241] [pass_manager] [trace] Registered pass (7) 'lowerallocastructs' - [Generic] Lower the stack allocations of structs to arrays
[2022-02-14 03:02:17.241] [pass_manager] [trace] Registered pass (8) 'match' - [ARM] Matches the IR to it's machine instructions and generates machine IR
[2022-02-14 03:02:17.241] [pass_manager] [trace] Registered pass (9) 'regalloc2' - [ARM] V2 Register allocation (linear scan)
[2022-02-14 03:02:17.241] [pass_manager] [trace] Registered pass (10) 'emit' - [ARM] Matches the IR to it's machine instructions and emits it as assembly to a file
[2022-02-14 03:02:17.242] [pass_manager] [trace] Pass: genlegal
[2022-02-14 03:02:17.242] [pass_manager] [trace] Validating pass 'genlegal'
[2022-02-14 03:02:17.242] [validate] [warning] instruction 'lfa' has no validation rules, ignoring
[2022-02-14 03:02:17.242] [pass_manager] [trace] Pass: structslegal
[2022-02-14 03:02:17.242] [pass_manager] [trace] Validating pass 'structslegal'
[2022-02-14 03:02:17.242] [validate] [warning] instruction 'lfa' has no validation rules, ignoring
[2022-02-14 03:02:17.242] [pass_manager] [trace] Pass: retcomb
[2022-02-14 03:02:17.242] [pass_manager] [trace] Validating pass 'retcomb'
[2022-02-14 03:02:17.242] [validate] [warning] instruction 'lfa' has no validation rules, ignoring
[2022-02-14 03:02:17.242] [pass_manager] [trace] Pass: genlower
[2022-02-14 03:02:17.242] [genlower] [debug] Found 1 instructions that require lowering
[2022-02-14 03:02:17.243] [pass_manager] [trace] Validating pass 'genlower'
[2022-02-14 03:02:17.243] [pass_manager] [trace] Pass: consthoist
[2022-02-14 03:02:17.243] [pass_manager] [trace] Validating pass 'consthoist'
[2022-02-14 03:02:17.243] [pass_manager] [trace] Pass: cconv
[2022-02-14 03:02:17.243] [pass_manager] [trace] Validating pass 'cconv'
[2022-02-14 03:02:17.243] [pass_manager] [trace] Pass: lowerallocastructs
[2022-02-14 03:02:17.243] [pass_manager] [trace] Validating pass 'lowerallocastructs'
[2022-02-14 03:02:17.243] [pass_manager] [trace] Pass: match
[2022-02-14 03:02:17.243] [critical] ******************** Internal Compiler Error ********************
[2022-02-14 03:02:17.243] [critical]     Unreachable code reached (paradoxical, i know)
[2022-02-14 03:02:17.243] [critical]
[2022-02-14 03:02:17.244] [critical]     File:        C:\helix\src\arm.cpp
[2022-02-14 03:02:17.244] [critical]     Line:        37
[2022-02-14 03:02:17.244] [critical]     Function:    GetMachineMode
[2022-02-14 03:02:17.244] [critical]     Explanation: no machine mode for type
[2022-02-14 03:02:17.244] [critical] ******************** Internal Compiler Error ********************

As per AAPCS32 - "char" is not signed

I've (subconsciously more than anything else) been operating under the assumption that char is signed, but AAPCS32 defines it as unsigned (https://github.com/ARM-software/abi-aa/blob/main/aapcs32/aapcs32.rst#811arithmetic-types).

Since the compiler doesn't really handle signedness (or even non int types :D) very well, this probably doesn't affect anything yet, but it's worth doing a pass over to double check

Machine instruction opcodes should not conflict with abstract IR opcodes

Assign indexes to the machine instruction opcodes so that they don't fall within the same range as the abstract instructions

Add convenience `Create*MachineInsn` functions.

These can be autogenerated & are a convenient way to generate machine instructions from their definitions in the machine description files.

Output IR control flow graph using Graphiz

Debug utility (like --emit-ir-post=xxxx) it would be good to be able to generate a visual graph of the control flow (with the basic blocks in each node) which can be processed by Graphiz.

Something like --dump-cfg-post=xxxx to emit the graph after the given pass.

Add pass for transforming from high IR (abstract) to low IR (real machine instructions)

Add pass that transforms the abstract IR instructions into machine instructions as defined by the patterns in arm.md (can leverage the existing matching infrastructure for this) but instead of writing text, replacing instructions.

This can probably replace the match pass and match can become final or something (like GCC)

Add Zero & Sign Extension Instructions

Would be a CompareInsn with the printed form of zext (for zero extension) and sext (for sign extension). Necessary to correctly & fully implement #10

Move the matching predicate & utility functions from `instructions.h` to `mir.h`

It's a bit messy with them being in instructions.h - they are only there because it was the other file I had open at the time... that's laziness for you.

They should be moved to mir.h.

The functions (as it stands) are:

stringify_operand
is_const_int_with_value
is_global
is_int
is_register
is_basic_block

In fact, all of these are reasoning about values & not instructions... sigh

Return structs from functions

Returning structs needs some special handling, see Parameter Passing - AAPCS32

https://github.com/ARM-software/abi-aa/blob/main/aapcs32/aapcs32.rst#64result-return

In short:

If it's smaller than (or equal to) 4 bytes in size (native register size) then it is stored directly in the r0 register (sign or zero extended if nessesary)
If it's larger than 4 bytes then the value is stored in memory and the address of that value is passed to the called function as a parameter (in r0)

Multidimensional arrays don't generate correct code

Given this source

void a()
{
	int a[10][10];
}

the following (incorrect) IR gets generated

function a(): void {
.0:
        stack_alloc [i32 x 10], %0:ptr
        ret
}

it should allocate 100 elements instead

Incorrect IR codegen for overflowing integer constants

Given this C code

int main() {
	unsigned char my_byte = 1000;
	return 0;
}

the following IR is generated

function main(): i32 {
.0:
        stack_alloc [i8 x 1], %0:ptr
        store 1000:i8, %0:ptr
        ret 0:i32
}

Of course you can't store 1000 in an i8, so this should wrap the integer around correctly 232.

(In fact clang actually warns about this, and gives this

C:\helix\.\testsuite\f.c:4:15: warning: implicit conversion from 'int' to 'u8' (aka 'unsigned char') changes value from
      1000 to 232 [-Wconstant-conversion]
        u8 my_byte = 1000;
           ~~~~~~~   ^~~~

Test f0012-integral-casts-small-to-big.c failing

[2022-01-11 16:24:34.233] [general] [info] Creating module from 'C:\helix\testsuite\f0\f0012-integral-casts-small-to-big.c'
[2022-01-11 16:24:34.235] [driver] [trace] End frontend compilation
[2022-01-11 16:24:34.235] [driver] [trace] Begin middle & backend compilation
[2022-01-11 16:24:34.235] [pass_manager] [trace] Registered pass (1) 'genlegal' - [Generic] Legalise illegal constructs IR to a legal equivilant
[2022-01-11 16:24:34.235] [pass_manager] [trace] Registered pass (2) 'structslegal' - [Generic] Legalise loading & storing struct types to/from virtual registers
[2022-01-11 16:24:34.235] [pass_manager] [trace] Registered pass (3) 'retcomb' - [Generic] Combine multiple returns into a singular exit point
[2022-01-11 16:24:34.236] [pass_manager] [trace] Registered pass (4) 'genlower' - [Generic] Lower high level IR constructs
[2022-01-11 16:24:34.236] [pass_manager] [trace] Registered pass (5) 'consthoist' - [ARM] Split and hoist constants to a form compatible with the ARM
[2022-01-11 16:24:34.236] [pass_manager] [trace] Registered pass (6) 'cconv' - [ARM] Lower IR to be compatible with the platform calling convention
[2022-01-11 16:24:34.236] [pass_manager] [trace] Registered pass (7) 'lowerallocastructs' - [Generic] Lower the stack allocations of structs to arrays
[2022-01-11 16:24:34.236] [pass_manager] [trace] Registered pass (8) 'regalloc' - [ARM] Register allocation
[2022-01-11 16:24:34.236] [pass_manager] [trace] Registered pass (9) 'match' - [ARM] Matches the IR to it's machine instructions and generates machine IR
[2022-01-11 16:24:34.236] [pass_manager] [trace] Registered pass (10) 'emit' - [ARM] Matches the IR to it's machine instructions and emits it as assembly to a file
[2022-01-11 16:24:34.237] [validate] [warning] instruction 'sext' has no validation rules, ignoring
[2022-01-11 16:24:34.237] [validate] [warning] instruction 'zext' has no validation rules, ignoring
[2022-01-11 16:24:34.237] [validate] [warning] instruction 'sext' has no validation rules, ignoring
[2022-01-11 16:24:34.237] [validate] [warning] instruction 'zext' has no validation rules, ignoring
[2022-01-11 16:24:34.237] [pass_manager] [trace] Pass: genlegal
[2022-01-11 16:24:34.237] [pass_manager] [trace] Validating pass 'genlegal'
[2022-01-11 16:24:34.237] [validate] [warning] instruction 'sext' has no validation rules, ignoring
[2022-01-11 16:24:34.238] [validate] [warning] instruction 'zext' has no validation rules, ignoring
[2022-01-11 16:24:34.238] [validate] [warning] instruction 'sext' has no validation rules, ignoring
[2022-01-11 16:24:34.238] [validate] [warning] instruction 'zext' has no validation rules, ignoring
[2022-01-11 16:24:34.238] [pass_manager] [trace] Pass: structslegal
[2022-01-11 16:24:34.238] [pass_manager] [trace] Validating pass 'structslegal'
[2022-01-11 16:24:34.238] [validate] [warning] instruction 'sext' has no validation rules, ignoring
[2022-01-11 16:24:34.238] [validate] [warning] instruction 'zext' has no validation rules, ignoring
[2022-01-11 16:24:34.238] [validate] [warning] instruction 'sext' has no validation rules, ignoring
[2022-01-11 16:24:34.239] [validate] [warning] instruction 'zext' has no validation rules, ignoring
[2022-01-11 16:24:34.239] [pass_manager] [trace] Pass: retcomb
[2022-01-11 16:24:34.239] [pass_manager] [trace] Validating pass 'retcomb'
[2022-01-11 16:24:34.239] [validate] [warning] instruction 'sext' has no validation rules, ignoring
[2022-01-11 16:24:34.239] [validate] [warning] instruction 'zext' has no validation rules, ignoring
[2022-01-11 16:24:34.239] [validate] [warning] instruction 'sext' has no validation rules, ignoring
[2022-01-11 16:24:34.239] [validate] [warning] instruction 'zext' has no validation rules, ignoring
[2022-01-11 16:24:34.240] [pass_manager] [trace] Pass: genlower
[2022-01-11 16:24:34.240] [genlower] [debug] Found 0 instructions that require lowering
[2022-01-11 16:24:34.240] [genlower] [debug] Found 0 instructions that require lowering
[2022-01-11 16:24:34.240] [genlower] [debug] Found 0 instructions that require lowering
[2022-01-11 16:24:34.240] [genlower] [debug] Found 0 instructions that require lowering
[2022-01-11 16:24:34.240] [pass_manager] [trace] Validating pass 'genlower'
[2022-01-11 16:24:34.240] [validate] [warning] instruction 'sext' has no validation rules, ignoring
[2022-01-11 16:24:34.240] [validate] [warning] instruction 'zext' has no validation rules, ignoring
[2022-01-11 16:24:34.241] [validate] [warning] instruction 'sext' has no validation rules, ignoring
[2022-01-11 16:24:34.241] [validate] [warning] instruction 'zext' has no validation rules, ignoring
[2022-01-11 16:24:34.241] [pass_manager] [trace] Pass: consthoist
[2022-01-11 16:24:34.241] [pass_manager] [trace] Validating pass 'consthoist'
[2022-01-11 16:24:34.241] [validate] [warning] instruction 'sext' has no validation rules, ignoring
[2022-01-11 16:24:34.241] [validate] [warning] instruction 'zext' has no validation rules, ignoring
[2022-01-11 16:24:34.241] [validate] [warning] instruction 'sext' has no validation rules, ignoring
[2022-01-11 16:24:34.241] [validate] [warning] instruction 'zext' has no validation rules, ignoring
[2022-01-11 16:24:34.241] [pass_manager] [trace] Pass: cconv
[2022-01-11 16:24:34.241] [pass_manager] [trace] Validating pass 'cconv'
[2022-01-11 16:24:34.241] [validate] [warning] instruction 'sext' has no validation rules, ignoring
[2022-01-11 16:24:34.241] [validate] [warning] instruction 'zext' has no validation rules, ignoring
[2022-01-11 16:24:34.241] [validate] [warning] instruction 'sext' has no validation rules, ignoring
[2022-01-11 16:24:34.242] [validate] [warning] instruction 'zext' has no validation rules, ignoring
[2022-01-11 16:24:34.242] [pass_manager] [trace] Pass: lowerallocastructs
[2022-01-11 16:24:34.242] [pass_manager] [trace] Validating pass 'lowerallocastructs'
[2022-01-11 16:24:34.242] [validate] [warning] instruction 'sext' has no validation rules, ignoring
[2022-01-11 16:24:34.242] [validate] [warning] instruction 'zext' has no validation rules, ignoring
[2022-01-11 16:24:34.242] [validate] [warning] instruction 'sext' has no validation rules, ignoring
[2022-01-11 16:24:34.242] [validate] [warning] instruction 'zext' has no validation rules, ignoring
[2022-01-11 16:24:34.242] [pass_manager] [trace] Pass: regalloc
[2022-01-11 16:24:34.242] [regalloc] [debug] @ i32=4 bytes, +4
[2022-01-11 16:24:34.242] [regalloc] [debug] @ i16=2 bytes, +6
[2022-01-11 16:24:34.242] [regalloc] [debug] @ i16=2 bytes, +8
[2022-01-11 16:24:34.242] [regalloc] [debug] @ i32=4 bytes, +12
[2022-01-11 16:24:34.243] [regalloc] [debug] @ i16=2 bytes, +14
[2022-01-11 16:24:34.243] [regalloc] [debug] Result Offset: 12 (Stack Frame: 16, Var Offset: 4)
[2022-01-11 16:24:34.243] [regalloc] [debug] Result Offset: 10 (Stack Frame: 16, Var Offset: 6)
[2022-01-11 16:24:34.243] [regalloc] [debug] Result Offset: 8 (Stack Frame: 16, Var Offset: 8)
[2022-01-11 16:24:34.243] [regalloc] [debug] Result Offset: 4 (Stack Frame: 16, Var Offset: 12)
[2022-01-11 16:24:34.243] [regalloc] [debug] Result Offset: 2 (Stack Frame: 16, Var Offset: 14)
[2022-01-11 16:24:34.243] [regalloc] [debug] @ i32=4 bytes, +4
[2022-01-11 16:24:34.243] [regalloc] [debug] @ i16=2 bytes, +6
[2022-01-11 16:24:34.243] [regalloc] [debug] @ i16=2 bytes, +8
[2022-01-11 16:24:34.243] [regalloc] [debug] @ i32=4 bytes, +12
[2022-01-11 16:24:34.243] [regalloc] [debug] @ i16=2 bytes, +14
[2022-01-11 16:24:34.243] [regalloc] [debug] Result Offset: 12 (Stack Frame: 16, Var Offset: 4)
[2022-01-11 16:24:34.244] [regalloc] [debug] Result Offset: 10 (Stack Frame: 16, Var Offset: 6)
[2022-01-11 16:24:34.244] [regalloc] [debug] Result Offset: 8 (Stack Frame: 16, Var Offset: 8)
[2022-01-11 16:24:34.244] [regalloc] [debug] Result Offset: 4 (Stack Frame: 16, Var Offset: 12)
[2022-01-11 16:24:34.244] [regalloc] [debug] Result Offset: 2 (Stack Frame: 16, Var Offset: 14)
[2022-01-11 16:24:34.244] [regalloc] [debug] @ i32=4 bytes, +4
[2022-01-11 16:24:34.244] [regalloc] [debug] @ i16=2 bytes, +6
[2022-01-11 16:24:34.244] [regalloc] [debug] @ i16=2 bytes, +8
[2022-01-11 16:24:34.244] [regalloc] [debug] @ i32=4 bytes, +12
[2022-01-11 16:24:34.244] [regalloc] [debug] @ i16=2 bytes, +14
[2022-01-11 16:24:34.244] [regalloc] [debug] Result Offset: 12 (Stack Frame: 16, Var Offset: 4)
[2022-01-11 16:24:34.245] [regalloc] [debug] Result Offset: 10 (Stack Frame: 16, Var Offset: 6)
[2022-01-11 16:24:34.245] [regalloc] [debug] Result Offset: 8 (Stack Frame: 16, Var Offset: 8)
[2022-01-11 16:24:34.245] [regalloc] [debug] Result Offset: 4 (Stack Frame: 16, Var Offset: 12)
[2022-01-11 16:24:34.245] [regalloc] [debug] Result Offset: 2 (Stack Frame: 16, Var Offset: 14)
[2022-01-11 16:24:34.245] [regalloc] [debug] @ i32=4 bytes, +4
[2022-01-11 16:24:34.245] [regalloc] [debug] @ i16=2 bytes, +6
[2022-01-11 16:24:34.245] [regalloc] [debug] @ i16=2 bytes, +8
[2022-01-11 16:24:34.245] [regalloc] [debug] @ i32=4 bytes, +12
[2022-01-11 16:24:34.245] [regalloc] [debug] @ i16=2 bytes, +14
[2022-01-11 16:24:34.245] [regalloc] [debug] Result Offset: 12 (Stack Frame: 16, Var Offset: 4)
[2022-01-11 16:24:34.245] [regalloc] [debug] Result Offset: 10 (Stack Frame: 16, Var Offset: 6)
[2022-01-11 16:24:34.246] [regalloc] [debug] Result Offset: 8 (Stack Frame: 16, Var Offset: 8)
[2022-01-11 16:24:34.246] [regalloc] [debug] Result Offset: 4 (Stack Frame: 16, Var Offset: 12)
[2022-01-11 16:24:34.246] [regalloc] [debug] Result Offset: 2 (Stack Frame: 16, Var Offset: 14)
[2022-01-11 16:24:34.246] [pass_manager] [trace] Validating pass 'regalloc'
[2022-01-11 16:24:34.246] [validate] [warning] instruction 'sext' has no validation rules, ignoring
[2022-01-11 16:24:34.246] [validate] [warning] instruction 'zext' has no validation rules, ignoring
[2022-01-11 16:24:34.246] [validate] [warning] instruction 'sext' has no validation rules, ignoring
[2022-01-11 16:24:34.246] [validate] [warning] instruction 'zext' has no validation rules, ignoring
[2022-01-11 16:24:34.246] [pass_manager] [trace] Pass: match
[2022-01-11 16:24:34.246] [general] [error] Failed to match instruction 'sext [i16 -> i32], r0:i16, r1:i32'
[2022-01-11 16:24:34.246] [critical] ******************** Internal Compiler Error ********************
[2022-01-11 16:24:34.246] [critical]     Unreachable code reached (paradoxical, i know)
[2022-01-11 16:24:34.247] [critical]
[2022-01-11 16:24:34.247] [critical]     File:        C:\helix\vs2022\src\arm-md.cpp
[2022-01-11 16:24:34.247] [critical]     Line:        609
[2022-01-11 16:24:34.247] [critical]     Function:    Helix::ARMv7::Expand
[2022-01-11 16:24:34.247] [critical]     Explanation: cannot expand instruction to machine ir, check arm.md
[2022-01-11 16:24:34.247] [critical] ******************** Internal Compiler Error ********************

Signed/Unsigned division needs to be handled differently

Currently there is only one variant of div but we should have different versions to handle unsigned & signed variations

Automated testing for different command line inputs

Now that the command line interface is getting a bit more complicated, it makes sense to have some tests for
this.
Can probably leverage Testify and the Flags property for this?

Rename helix-config.in.h -> helix-config.h.in

This doesn't matter at all really, it just annoys me every time I see it

Better error reporting for machine description parsing

Currently the errors reported by the MachineDescription are terrible, just unchecked exceptions. Ideally errors should have at least:

A line number (with column being ideal as well)
A useful description.

Improve unit testing situation

There is a lot more that could be unit tested, and the infrastructure for this should be a lot better.

Backend code generation rewrite to represent machine instructions in the IR

Currently machine instructions are only represented at the very last level - as text.
This would see those machine instructions represented in the (a) IR somehow.

This representation could be generated from the existing patterns in arm.md (with a bit of adjustment):

(define-insn "add_r32r32"
	[(kInsn_IAdd
		(match_operand:i32 0 "register")
		(match_operand:i32 1 "register")
		(match_operand:i32 2 "register"))]
	"add {2}, {0}, {1}")

The opcode of the machine instruction could be specified as the first given field (the name, in this case add_r32r32).
The pattern to used to generate the machine instruction (from abstract IR) is the same as normal, given in the second field).
The assembly text to generate from this machine instruction is given as the last instruction.
Operands to the machine instruction could be parsed from the parameters given in the assembly text string.

Sub Tasks

Unsupported C features

This is a working list of all features that are not supported:

Generate assembly from machine IR instead of abstract IR

Rework match pass so that it generates assembly text based off the machine instructions rather than the abstract IR instructions.

The match pass should probably become final and match will be repurposed to translate from high level IR to low level IR

Move register allocation so that it happens after match pass

This would allow the match pass to take advantage of the flexible nature of virtual registers for example

Add equivalent of GCCs `define_expand`.

So that a machine instruction pattern can be used to generate multiple IR machine instructions. This necessary for instructions such as icmp or cbr which currently expand to multiple assembly instructions

First test occasionally fails the first time running the testsuite for the first time

Sporadic failure of the first testcase when running the testsuite for the first time in a while.

The fact that it only fails the first time & not subsequent times during the same "session" are going to make this a bugger to repro & debug.

Maybe something is timing out (first time running programs often take longer to startup, maybe some caching of behalf of Windows or something?)

Loading global variables with sizes < 32 bits will load a full 32 bits instead of the data size

This is because the register allocator likes to use i32 for everything and I'm guessing ldr loads a full word (32 bits?) See how clang/gcc handle this, maybe it's worth using .4byte for every global, even those with smaller types (would save this problem entirely)

Code generation support for procedure calls

Big catch all task for implementing code gen support for calling functions.

Handling parameters to functions
Handling passing parameters to functions
Handling returning values from functions
Handling the return values returned from called functions.

ABI standard is AACPS32 (https://github.com/ARM-software/abi-aa/blob/main/aapcs32/aapcs32.rst)

Test f5004-legalise-struct-initialisers.c fail

[2022-01-11 16:21:28.319] [general] [info] Creating module from 'C:\helix\testsuite\f5\f5004-legalise-struct-initialisers.c'
[2022-01-11 16:21:28.320] [driver] [trace] End frontend compilation
[2022-01-11 16:21:28.321] [driver] [trace] Begin middle & backend compilation
[2022-01-11 16:21:28.321] [pass_manager] [trace] Registered pass (1) 'genlegal' - [Generic] Legalise illegal constructs IR to a legal equivilant
[2022-01-11 16:21:28.321] [pass_manager] [trace] Registered pass (2) 'structslegal' - [Generic] Legalise loading & storing struct types to/from virtual registers
[2022-01-11 16:21:28.322] [pass_manager] [trace] Registered pass (3) 'retcomb' - [Generic] Combine multiple returns into a singular exit point
[2022-01-11 16:21:28.322] [pass_manager] [trace] Registered pass (4) 'genlower' - [Generic] Lower high level IR constructs
[2022-01-11 16:21:28.322] [pass_manager] [trace] Registered pass (5) 'consthoist' - [ARM] Split and hoist constants to a form compatible with the ARM
[2022-01-11 16:21:28.322] [pass_manager] [trace] Registered pass (6) 'cconv' - [ARM] Lower IR to be compatible with the platform calling convention
[2022-01-11 16:21:28.322] [pass_manager] [trace] Registered pass (7) 'lowerallocastructs' - [Generic] Lower the stack allocations of structs to arrays
[2022-01-11 16:21:28.322] [pass_manager] [trace] Registered pass (8) 'regalloc' - [ARM] Register allocation
[2022-01-11 16:21:28.322] [pass_manager] [trace] Registered pass (9) 'match' - [ARM] Matches the IR to it's machine instructions and generates machine IR
[2022-01-11 16:21:28.322] [pass_manager] [trace] Registered pass (10) 'emit' - [ARM] Matches the IR to it's machine instructions and emits it as assembly to a file
[2022-01-11 16:21:28.322] [pass_manager] [trace] Pass: genlegal
[2022-01-11 16:21:28.323] [pass_manager] [trace] Validating pass 'genlegal'
[2022-01-11 16:21:28.323] [validate] [warning] instruction 'lfa' has no validation rules, ignoring
[2022-01-11 16:21:28.323] [validate] [warning] instruction 'lfa' has no validation rules, ignoring
[2022-01-11 16:21:28.323] [validate] [warning] instruction 'lfa' has no validation rules, ignoring
[2022-01-11 16:21:28.323] [validate] [warning] instruction 'lfa' has no validation rules, ignoring
[2022-01-11 16:21:28.323] [validate] [warning] instruction 'lfa' has no validation rules, ignoring
[2022-01-11 16:21:28.323] [pass_manager] [trace] Pass: structslegal
[2022-01-11 16:21:28.323] [pass_manager] [trace] Validating pass 'structslegal'
[2022-01-11 16:21:28.323] [validate] [warning] instruction 'lfa' has no validation rules, ignoring
[2022-01-11 16:21:28.323] [validate] [warning] instruction 'lfa' has no validation rules, ignoring
[2022-01-11 16:21:28.323] [validate] [warning] instruction 'lfa' has no validation rules, ignoring
[2022-01-11 16:21:28.324] [validate] [warning] instruction 'lfa' has no validation rules, ignoring
[2022-01-11 16:21:28.324] [validate] [warning] instruction 'lfa' has no validation rules, ignoring
[2022-01-11 16:21:28.324] [pass_manager] [trace] Pass: retcomb
[2022-01-11 16:21:28.324] [pass_manager] [trace] Validating pass 'retcomb'
[2022-01-11 16:21:28.324] [validate] [warning] instruction 'lfa' has no validation rules, ignoring
[2022-01-11 16:21:28.324] [validate] [warning] instruction 'lfa' has no validation rules, ignoring
[2022-01-11 16:21:28.324] [validate] [warning] instruction 'lfa' has no validation rules, ignoring
[2022-01-11 16:21:28.324] [validate] [warning] instruction 'lfa' has no validation rules, ignoring
[2022-01-11 16:21:28.324] [validate] [warning] instruction 'lfa' has no validation rules, ignoring
[2022-01-11 16:21:28.325] [pass_manager] [trace] Pass: genlower
[2022-01-11 16:21:28.325] [genlower] [debug] Found 5 instructions that require lowering
[2022-01-11 16:21:28.325] [pass_manager] [trace] Validating pass 'genlower'
[2022-01-11 16:21:28.325] [pass_manager] [trace] Pass: consthoist
[2022-01-11 16:21:28.325] [pass_manager] [trace] Validating pass 'consthoist'
[2022-01-11 16:21:28.325] [pass_manager] [trace] Pass: cconv
[2022-01-11 16:21:28.325] [critical] ******************** Internal Compiler Error ********************
[2022-01-11 16:21:28.325] [critical]     Assertion Failed!
[2022-01-11 16:21:28.325] [critical]
[2022-01-11 16:21:28.325] [critical]     File:      C:\helix\src\lower.cpp
[2022-01-11 16:21:28.325] [critical]     Line:      379
[2022-01-11 16:21:28.325] [critical]     Function:  Helix::CConv::Execute
[2022-01-11 16:21:28.326] [critical]     Condition: ARMv7::TypeSize(returnValue->GetType()) <= r0Size
[2022-01-11 16:21:28.326] [critical]     Reason:    return value can't fit in output register
[2022-01-11 16:21:28.326] [critical] ******************** Internal Compiler Error ********************

 	ucrtbase.dll!00007ffa9fc1286e()	Unknown
 	hxc.exe!llvm::Error::fatalUncheckedError(void)	C++
 	[Inline Frame] hxc.exe!llvm::Error::assertIsChecked() Line 266	C++
 	[Inline Frame] hxc.exe!llvm::Error::{dtor}() Line 228	C++
 	hxc.exe!Helix::Frontend::Run(int argc, const char * * argv) Line 1699	C++
 	hxc.exe!main(int argc, const char * * argv) Line 11	C++
 	[External Code]

Not a massive problem, but recording nonetheless

Match against multi instruction patterns in arm.md

e.g.

(define-insn "load_sgptr"
	[(kInsn_Load
		(match_operand:ptr 0 "global")
		(match_operand:i32 1 "register"))
         (kInsn_SignExtend
		(match_operand:i8 0 "register")
		(match_operand:i32 1 "register"))]
	"movw {1}, :lower16:{0}"
	"movt {1}, :upper16:{0}"
	"ldrsb {1}, [{1}]")

Required for #10 - so that the correct load instruction (e.g. ldrsb, ldrb, ldrsh, ldrh etc...) can be generated when loading from globals that are smaller than 32 bits in size)