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View Code? Open in Web Editor NEWA stream to RTL compiler based on MLIR and CIRCT
License: Other
A stream to RTL compiler based on MLIR and CIRCT
License: Other
This will require a change in CIRCT, as these patterns aren't accessible form the outside.
We have to ensure that we fix the EOS
semantics and then we have to either update the driver or the operators.
There are two approaches I can see here:
EOS
value.Supporting calls can be helpful if one wants to reuse complicated snippets and external functions could be implemented directly in verilog.
I'm not sure if all operations do skip their lambdas if an EOS was sent. As the computation might be complex, or even result in infinite loops, we have to be sure to skip the computation.
Fixing the normal tests was forgotten.
On my local machine, the integration test for complex.mlir
causes a assertion violation in malloc:
Exit Code: 1
Command Output (stderr):
--
Vdriver: malloc.c:2617: sysmalloc: Assertion `(old_top == initial_top (av) && old_size == 0) || ((unsigned long) (old_size) >= MINSIZE && prev_inuse (old_top) && ((unsigned long) old_end & (pagesize - 1)) == 0)' failed.
/home/dinistro/mlir-dev/thesis/integration_test/Dialect/Stream/complex.mlir:16:11: error: CHECK: expected string not found in input
// CHECK: Element={{.*}}12
^
<stdin>:1:1: note: scanning from here
make: Entering directory '/home/dinistro/mlir-dev/circt/build/integration_test/Dialect/Stream/complex.mlir.tmp.sv.d/obj_dir'
^
<stdin>:1:59: note: possible intended match here
make: Entering directory '/home/dinistro/mlir-dev/circt/build/integration_test/Dialect/Stream/complex.mlir.tmp.sv.d/obj_dir'
^
Input file: <stdin>
Check file: /home/dinistro/mlir-dev/thesis/integration_test/Dialect/Stream/complex.mlir
-dump-input=help explains the following input dump.
Input was:
<<<<<<
1: make: Entering directory '/home/dinistro/mlir-dev/circt/build/integration_test/Dialect/Stream/complex.mlir.tmp.sv.d/obj_dir'
check:16'0 X~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ error: no match found
check:16'1 ? possible intended match
2: g++ -I. -MMD -I/home/dinistro/mlir-dev/circt/ext/share/verilator/include -I/home/dinistro/mlir-dev/circt/ext/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++14 -Os -c -o driver.o /home/dinistro/mlir-dev/thesis/integration_test/Dialect/Stream/driver.cpp
check:16'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3: /usr/bin/perl /home/dinistro/mlir-dev/circt/ext/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vdriver.cpp Vdriver_handshake_buffer_in_tuple_ui64_ui1_out_tuple_ui64_ui1_2slots_fifo.cpp Vdriver__Slow.cpp Vdriver_handshake_buffer_in_tuple_ui64_ui1_out_tuple_ui64_ui1_2slots_fifo__Slow.cpp Vdriver__Syms.cpp > Vdriver__ALL.cpp
check:16'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
4: g++ -I. -MMD -I/home/dinistro/mlir-dev/circt/ext/share/verilator/include -I/home/dinistro/mlir-dev/circt/ext/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++14 -Os -c -o Vdriver__ALL.o Vdriver__ALL.cpp
check:16'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
5: Archive ar -cr Vdriver__ALL.a Vdriver__ALL.o
check:16'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
6: g++ driver.o verilated.o Vdriver__ALL.a -o Vdriver
check:16'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.
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>>>>>>
This happens for the allFIFO
RUN, but I can somehow not reproduce this outside of llvm-lit
.
As of now, the init ctrl signal/token is only used in the create
operation. To get consistent lowerings we have to decide how this signal is used and in what order the operations receive this signal.
Furthermore, it's not yet clear if the result should be returned or not and what the final return
will output.
See the lowering of sink
and how it gives a weird handling of the ctrl signal.
I recently figured out how we can resolve the longstanding issue, but cannot do the change right now.
Change SOURCE to BUILD on the following lines
https://github.com/Dinistro/circt-stream/blob/main/test/CMakeLists.txt#L23
CIRCTs cocotb driver gets changed and fixed frequently. Having a copy of it in this repo is a bad idea. Instead, we should use the provided one and just add additional helpers to it.
Currently, all the lambdas provided to operations are pure. There is no way to somehow explicitly interact with external memory in any of the operations at this point.
Changing the buffering strategy from all
to allFIFO
causes at least some integration tests to break.
Reproducible by changing the strategy in the combine.mlir
test.
This might be caused by the missing task pipeline safety transformation. See #31
Edit: This seems to be caused by create
already. Thus all following operations will consume invalid streams.
Note: breaks for cylces
strategy as well.
The signature of create
has only one ctrl signal.
Related to #26
Most of this will have to be added to CIRCT
Executing llvm-lit
on a testing directory causes the following crash:
llvm-lit: /home/dinistro/mlir-dev/circt/llvm/llvm/utils/lit/lit/TestingConfig.py:135: fatal: unable to parse config file '/home/dinistro/mlirdev/thesis/integration_test/lit.cfg.py', traceback: Traceback (most recent call last):
File "/home/dinistro/mlir-dev/circt/llvm/llvm/utils/lit/lit/TestingConfig.py", line 124, in load_from_path
exec(compile(data, path, 'exec'), cfg_globals, None)
File "/home/dinistro/mlir-dev/thesis/integration_test/lit.cfg.py", line 23, in <module>
config.test_format = lit.formats.ShTest(not llvm_config.use_lit_shell)
AttributeError: 'NoneType' object has no attribute 'use_lit_shell'
I have the same issue in CIRCT, but it works in MLIR.
Having only one handshaking for both the data elements and the EOS signal should simplify some of the lowerings while also providing a simpler interface for potential users.
This should also fix #2
Currently, it is possible to construct input IR that declares non-stream SSA values at the top level and references them from within stream operations.
It seems that calling the StdToHandshake's lowerRegion
can cause UB. This happens when a legalization check runs over erased operation it didn't get informed about.
Currently, the stream-to-handshake
implementation seems to have a lot of redundant code. We should try to find common patterns and factor certain parts out.
I tried that before but had some issues, but since then parts of the structure have changed.
There were some breaking changes in the handshake lowering. Thus, it would make sense to bump this repo to the newest CIRCT commit.
Now that handshake
has the possibility to produce ctrl
signals with a join operation, it might make sense to drop the additional input signal.
This change would simplify the lowerings substantially, as we would get a 1 to 1 type conversion, compared to a 1 to 2. So we could finally rely on the type converter and the adaptors to work as expected.
There seems to be an issue with an inclusion of the following file
#include"mlir/Tools/mlir-opt/MlirOptMain.h"
It seems that split
emits the first tuple multiple times. This behaviour can be observed in the integration tests, thus the root of this issue might be in the system verilog drivers.
It seems that the test driver that reports outgoing elements prints some result twice due to a bug.
To make the deployed circuits more flexible, it might make sense to allow reading in external values. This can either be done in an initialization phase or with additional stream inputs.
The repo is currently missing a LICENSE file. Should we copy the same Apache 2.0 with LLVM exceptions as from https://github.com/llvm/circt/blob/main/LICENSE or https://github.com/llvm/llvm-project/blob/main/llvm/LICENSE.TXT ?
The lowerings create new functions and thus require unique names for them. CIRCT has something called a SymbolCache
that might help here.
It seems that the table-gen files might be missing.
In file included from /home/dinistro/mlir-dev/thesis/lib/Conversion/StreamToHandshake/StreamToHandshak
e.cpp:17:
/home/dinistro/mlir-dev/thesis/include/circt-stream/Dialect/Stream/StreamDialect.h:14:10: fatal error:
'circt-stream/Dialect/Stream/StreamOpsDialect.h.inc' file not found
#include "circt-stream/Dialect/Stream/StreamOpsDialect.h.inc"
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 error generated.
That change would require graph regions.
This should eliminate version confusions later on.
Lowering regions that have multiple basic blocks fails due to not removing the basic blocks. Resolving this will either require to expose the removeBasicBlocks
in CIRCT or copy it into this repo.
Applying steam-opt --convert-stream-to-handshake
on the following input causes a segfault:
func.func @top() -> !stream.stream<i64> {
%in = stream.create !stream.stream<i64> [1,2,3]
%left, %right = stream.split(%in) : (!stream.stream<i64>) -> (!stream.stream<i64>, !stream.stream<i64>) {
^0(%val : i64):
%0 = arith.constant 10 : i64
%r = arith.addi %0, %val : i64
stream.yield %0, %r : i64, i64
}
%out = stream.reduce(%left) {initValue = 0 : i64}: (!stream.stream<i64>) -> !stream.stream<i64> {
^0(%acc: i64, %val: i64):
%r = arith.addi %acc, %val : i64
stream.yield %r : i64
}
stream.sink %right : !stream.stream<i64>
return %out : !stream.stream<i64>
}
It seems that the segfault is trigger in the destructor of the mlir::FrozenRewritePatternSet
.
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