This is a collection of electronic design automation surveys, courses, and open source tools.

• [Books and Surveys]
• [Courses and Tutorials]
• [Workshops on Open Source EDA]
• [Open Source Tools (code available)]
• [Open Access Tools (binary only)]

• ICCAD 2015 Session 3D From EDA to DA: Can We Evolve Beyond Our E-Roots?
• DAC-2015 DA Perspective Challenge
• CCC Visioning Activity 2014 Extreme Scale Design Automation
• 2019 Third Party CAD Tools for FPGA Design—A Survey of the Current Landscape
• 2018 Opportunities for Machine Learning in IC Physical Design

• 2003 Synthesis and Optimization of Digital Circuits
• 2018 Logic Synthesis for Established and Emerging Computing

• 2015 Progress and Challenges in VLSI Placement Research

• 2001 A Survey on Multi-net Global Routing for Integrated Circuits
• 2008 The coming of age of (academic) global routing

• Rob A. Rutenbar, VLSI CAD Part I: Logic and VLSI CAD Part II: Layout
• Sung Kyu Lim, ECE6133: Physical Design Automation of VLSI Systems
• David Z. Pan, EE 382V: VLSI Physical Design Automation
• Sanjit A. Seshia, EECS 219C: Formal Methods: Specification, Verification, and Synthesis
• Chung-Kuan Cheng, CSE245: Computer Aided Circuit Simulation and Verification
• Gogul Ilango's notes ASIC Design

• DAC Birds of a Feather: Open Source Academic EDA Software
  • DAC 2019 BOF, June 5, 2019; Las Vegas, NV, USA.
• OSDA: Workshop on Open Source Design Automation
  • OSDA 2019, co-located with DATE, March 29, 2019; Florence, Italy.
• WOSET: Workshop on Open-Source EDA Technology
  • WOSET 2018, co-located with ICCAD, Nov 8, 2018; San Diego, CA, USA.
• ORConf: The open source digital design conferece
  • ORConfs: 2018 | 2017 | 2016 | 2015 | 2014 | 2013 | 2012

• qflow (Dr. R. Timothy Edwards), GNU General Public License
  • A Digital Flow using Open Source EDA Tools.
• VSDFLOW (VLSI System Design), "available for download for FREE"
  • An automated RTL-to-GDS flow for programmers, hobbyists, and small-scale entrepreneurs.
• OpenRoad (UCSD), various licenses (BSD 2-Clause, BSD 3-Clause, GPL 3.0, ISC, etc.)
  • Aim to develop open-source tools that achieve autonomous, 24-hour layout implementation.
• Ophidian (UFSC)
  • An open-source library for physical design research and teaching.
• Rsyn (FURG)
  • An Extensible Physical Synthesis Framework.
• gEDA
  • Working on a full GPL'd suite and toolkit of Electronic Design Automation tools.

• VTR (Toronto)
  • An CAD flow tool for FPGA including ODIN-II, ABC, VPR place, and VPR route.
• RapidWright (Xilinx)
  • Provide Vivado Interface for users to build customized FPGA implementations.
  • Similar projects: Torc, RapidSmith, and RapidSmith2
• IceStorm (Clifford Wolf)
  • Aims at reverse engineering and documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.
  • A working fully open source flow with Yosys and Arachne-pnr.
• FPGA CAD Framework (Ghent Univ.)
  • A Java framework focused on rapid prototyping of new CAD algorithms for FPGA compilation.
• Rebit
  • A low level configuration analysis and for the debugging and validation of the bitstream files of architectures that exploit dynamic partial reconfiguration on Xilinx FPGAs.
• Sdaccel-chisel-integration
  • A wrapper in Chisel for using RTL kernels into SDAccel 2017.1.
• hCODE (Kumamoto Univ.)
  • A tool to simplify the creation, sharing, and software integration of FPGA hardware accelerators.
• Automata to Routing (U.Va.)
  • An open-source toolchain to design and evaluate island style spatial automata processing architectures.
• DATuner (Cornell, PKU)
  • A parallel bandit-based approach for autotuning FPGA compilation.

• LegUp (Toronto)
  • A high-level synthesis tool to improve C to Verilog synthesis without building an infrastructure from scratch.
• GAUT (Université Bretagne Sud)
  • A high-level synthesis tool from algorithm to hardware architecture.
• PandA (Politecnico di Milano)
  • A usable framework that will enable the research of new ideas in the HW-SW Co-Design field.
• FCUDA (ADSC High Level Synthesis Team)
  • A source-to-source transformation framework that takes CUDA kernels with FCUDA annotation pragmas as input and produces a synthesizable C code.

• HeteroCL (Cornell, UCLA)
  • A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing.
• Chisel (Berkeley)
  • A hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.
• FIRRTL (Berkeley)
  • An intermediate representation (IR) for digital circuits designed as a platform for writing circuit-level transformations.
• BAG: Berkeley Analog Generator (Berkeley)
  • A Python-based circuit design platform that aims to automate analog circuit design, but at the same time give the user full visibility and control over every step in the design flow.

• ABC (Berkeley)
  • A sequential logic synthesis and formal verification tool.
• LLDHL
  • A logic synthesis and manipulation infrastructure for FPGAs.
• Yosys (Clifford Wolf)
  • A framework for Verilog RTL synthesis, used by qflow and OpenROAD

• DREAMPlace (UT Austin)
  • A GPU-accelerated analytical placement tool.
• OpenROAD RePlAce (UCSD)
  • A global placement tool with advancing solution quality and routability validation.
• RippleFPGA (CUHK)
  • A simultaneous pack-and-place algorithm for FPGA.
• arachne-pnr
  • A place and route tool for FPGAs.
• nextpnr
  • A vendor neutral, timing driven, FOSS FPGA place and route tool.
• qflow Graywolf
  • A placement tool in VLSI design and used together with qflow.

• qflow Qrouter
  • A detailed router based on the standard Lee maze router algorithm.
• Dr. CU (CUHK)
  • VLSI detailed routing tool.
• FGR (UMich)
  • A global router based on Lagrange Multipliers and won the 1st place in ISPD 2007 contest.
• BoxRouter (UT Austin)
  • A global router for ultimate routability and won the 2nd place in ISPD 2007 contest.
• NTHU-Route (NTHU)
  • A fast and stable global router and won the 1st place in ISPD 2008 contest.
• FastRoute (Iowa State)
  • A global routing tool for VLSI back-end design.
• FLUTE (Iowa State)
  • A very fast and accurate technique for rectilinear Steiner minimal tree (RSMT) construction.
• SALT (CUHK)
  • A tool for generating VLSI routing topology.

• Verilator
  • A fast free Verilog/SystemVerilog simulator.
• GHDL
  • An open-source simulator for the VHDL language.
• FreeHDL
  • A free, open source, GPL'ed VHDL simulator for Linux.
• TkGate
  • A digital circuit editor and simulator with a Tcl/Tk-based interface.

• OpenTimer (UIUC)
  • A High-Performance Timing Analysis Tool for VLSI Systems.
• OpenROAD OpenSTA
  • A gate level static timing verifier.

• ngspice
  • Open source spice simulator.
• SPICE (Berkeley)
  • A general-purpose circuit simulation program for nonlinear dc, nonlinear transient, and linear ac analyses.
• mixedsim (Isotel)
  • Mixed signal simulation with Verilog.
• Gnucap: GNU Circuit Analysis Package
  • A modern "post-spice" analog and mixed signal circuit simulator.
• Qucs: Quite Universal Circuit Simulator
  • Setup a circuit with a graphical user interface (GUI) and simulate the large-signal, small-signal and noise behaviour of the circuit.
• Xyce (Sandia NL)
  • An open source, SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms.

• FreeCAD
  • An open-source parametric 3D modeler made primarily to design real-life objects of any size.
• Fast Field Solvers (FastFieldSolvers)
  • The "SPICE" of the ElectroMagnetic world.
  • E.M. Workbench, FasterCap, FastCap2, FastHenry2, FastModel

• Netgen
  • A circuit netlist comparison (LVS) and netlist conversion tool.
• SymbiYosys (Clifford Wolf)
  • Front-end for Yosys-based formal verification flows.

• Magic
  • A VLSI layout editor, extraction, and DRC tool.
• KLayout
  • A high performance layout viewer and editor.
• OpenMPL
  • An open source layout decomposition tool.

• FreePDK (NC State)
  • An open-source, Open-Access-based PDK for the 45nm technology node and the Predictive Technology Model.
• POSH OpenFPGA (UofU)
  • A FPGA IP generator using XML-based architecture description including three parts: FPGA-Verilog, FPGA-SPICE, FPGA-Bitstream.
• OpenRAM (UCSC)
  • An open-source memory compiler for VLSI circuits.
• LibreCores
  • A digital hardware design community for creating and distributing IP cores in the open source spirit.
• OpenCores
  • The reference community for Free and Open Source gateware IP cores.

• HDL (Verilog, VHDL, etc.)
  • Icarus Verilog, a Verilog simulation and synthesis tool compiling source code written in Verilog (IEEE-1364) into some target format
  • verilog-parser, a parser for the IEEE 1364-2001 verilog standard
  • pyverilog, a hardware design processing toolkit for Verilog HDL including verilog parser, dataflow analyzer, control-flow analyzer and code generator
  • hdlparse, a simple package implementing a rudimentary parser for VHDL and Verilog
• LEF/DEF
  • Si2 LEF/DEF Toolkit
  • RazKarapetyan's LEF/DEF parser
  • Tri Minh Cao's LEF parser
• Liberty
  • Mirror of Synopsys's Liberty parser library
• SDC
  • Synopsys TAP-in SDC parser
  • dalance's SDC parser

• DATC Robust Design Flow (IEEE CEDA)
• VLSI CAD Bookshelf 2

• FuseSoC
  • A package manager and a set of build tools for HDL code.

• ePlace (UCSD)
  • An electrostatics based placer using Nesterov's method.
• NTUplace (NTU)
  • A ratio partitioning based placer for large-scale mixed-size designs.
• FastPlace (Iowa State)
  • An Analytical Placer for Large-scale VLSI Circuits.
• mPL6 (UCLA)
  • Constrained placement by multilevel optimization.
• Dragon (UCLA)
  • A fast, effective standard-cell placement tool for both variable-die and fixed-die ASIC design.
• Capo (UMich)
  • A fast and high-quality routability-driven placer for standard-cell ASICs.

• Liberty
  • Liberty::Parser, a Perl wrapper for Synopsys's Open Liberty Project