AIM:
To implement D flipflop using verilog and validating their functionality using their functional tables
SOFTWARE REQUIRED:
Quartus prime
THEORY
D Flip-Flop
D flip-flop operates with only positive clock transitions or negative clock transitions. Whereas, D latch operates with enable signal. That means, the output of D flip-flop is insensitive to the changes in the input, D except for active transition of the clock signal. The circuit diagram of D flip-flop is shown in the following figure.
This circuit has single input D and two outputs Qtt & Qtt’. The operation of D flip-flop is similar to D Latch. But, this flip-flop affects the outputs only when positive transition of the clock signal is applied instead of active enable. The following table shows the state table of D flip-flop.
Therefore, D flip-flop always Hold the information, which is available on data input, D of earlier positive transition of clock signal. From the above state table, we can directly write the next state equation as Qt+1t+1 = D
Next state of D flip-flop is always equal to data input, D for every positive transition of the clock signal. Hence, D flip-flops can be used in registers, shift registers and some of the counters.
Procedure
/* write all the steps invloved */
PROGRAM
Program for flipflops and verify its truth table in quartus using Verilog programming.
Developed by: DHARANI DHARAN K
RegisterNumber: 21223040036
input D,Clock;
output reg Q,Qbar;
always @ (negedge Clock)// use negative edge clock for triggereing condition
//compute D flipflop logic here
begin
Q=D;
Qbar=~D;
end
endmodule
RTL LOGIC FOR FLIPFLOPS
TIMING DIGRAMS FOR FLIP FLOPS
RESULTS
Thus the program to implement a D flipflop using verilog and validating their functionality using their functional tables.