Comments (1)
Minimized:
import dfhdl.*
class DictControl(val fetch_count: Int <> CONST) extends RTDesign():
val c = Boolean <> IN
val matching = Bits(fetch_count) <> VAR
if (c) matching(0) := 1
@main def main = DictControl(fetch_count = 2).compile
from dfhdl.
Related Issues (15)
- Compile error when using struct fields in nested if HOT 7
- Incorrect conversion of signed SRA and std_logic_vector SRL for VHDL HOT 1
- Missing conversion functions in VHDL pkg
- Array type is not generated for vectors (VHDL) HOT 3
- to_slv function missing for std_logic
- Can't assign to indexed Bits(1) variable
- Verilog doesn't use arithmetic right shift for SInt HOT 1
- prev/prev(1) is not correctly assigned to VARs HOT 2
- Missing functions in std_logic_vector to struct conversion
- Error in VHDL code gen when vectors are part of struct
- VHDL array indexing requires to_integer function
- Double struct declaration for VHDL
- Clock and reset signals of submodules declared but not assigned in RTDesign HOT 2
- Clock and reset missing in generated files when top level is combinational HOT 2
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from dfhdl.