Comments (7)
@MartinC45 Hi. Thank you very much for trying out DFHDL and reporting this!
Would fix this very soon.
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BTW, I have a question, if you don't mind answering. Currently our documentation shows nothing about the struct feature (one of the reasons is to first flush out most of the bugs ourselves). How did you go about learning this feature?
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Hi, no problem and sure. I found it in some slides you shared on Reddit some time ago. Should I wait until the release of the full documentation before opening further issues?
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Feel free to open issues. Your time is valuable and I don't want to waste it, and I want your experience to be fun. But if you like being on the cutting bleeding edge, hack away :)
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This is a more general problem in the RT to ED compilation stage, and fails in this example:
class GlobCounter(val width: Int <> CONST) extends RTDesign:
val t = Bit <> IN
val cnt = UInt(width) <> OUT.REG init 0
// doesn't work
if (t || t)
if (t || t)
cnt.din := cnt + 1
end GlobCounter
Should be resolved tomorrow.
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@MartinC45 v0.4.4 fixes this issue.
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Yes, it works nicely now. Thanks!
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