cwfletcher / stt Goto Github PK

Build fails with this error

Exception: MI_example-cache.sm:401: Error: Invalid method call: Type 'Sequencer' does not have a method evictionCallback, 'evictionCallback_Addr' nor '':

Even though there exists a method defined in ruby/system/Sequencer*

any idea how to fix this?

I'm reading the implementation about how to control delaying TLB lookup. According to current implementation, STT does not use readyToExpose in InvisiSpec anymore before TLB lookup. That's to say, the status of isSPEC() in request is not set if the isInvisibleSpec flag is not enabled. Then, the TLB lookup is not delayed.

If I want to enable delaying TLB lookup, is it necessary to enable the isInvisibleSpec flag during simulation?

Waiting for your response. Thank you very much!

I have Python 2.7.17 and also have scons installed which are working fine for gem5 simulator. When I am running this stt or sdo I am getting this error. Please suggest!

** Error loading site_init file './site_scons/site_init.py':
File "./site_scons/site_init.py", line 55

print """

For more details, see:
http://gem5.org/Dependencies
"""

^

SyntaxError: invalid syntax

Hello! I want to modify the code to only block the attacks using memory hierachy as the covert channel. So I modify the function "BaseDynInst::readyToIssue_UT()" in base_dyn_impl.hh. Is that correct to achieve my prospect?

/*** [Jiyong,STT] ***/
template <class Impl>
bool
BaseDynInst<Impl>::readyToIssue_UT() const
{
    bool ret = status[CanIssue];
    if (cpu->moreTransmitInsts == 1) {
        // consider int div and fp div
        if (opClass() == IntDivOp   ||
            opClass() == FloatDivOp ||
            opClass() == FloatSqrtOp)
            ret = ret && (!instFlags[IsArgsTainted]);
    }
    else if (cpu->moreTransmitInsts == 2) {
        if (opClass() == IntDivOp ||
            isFloating())
            ret = ret && (!instFlags[IsArgsTainted]);
    }
    // block memory hierachy covert channel >>>
    else if (cpu->moreTransmitInsts == 3) {
        if (this->isMemRef())
            ret = ret && (!instFlags[IsArgsTainted]);
    }
    // <<<
    else {
        assert (0);
    }
    return ret;
}

In addition, I wonder why the original code for dealing with different "moreTransmitInsts" values (1 & 2) does not include the memory instructions.

I know the STT has a strong defense against Spectre attacks, but is it a good defense against Meltdown and so on？

How can we perform a full system simulation with STT add-ons? Is it supported?

I tried different kernel versions through the regular full system simulation flow and the simulation runs into boot panic.

Hi, I have tried spectre code on unsafe mode, but it does not work. Do you have the sample spectre attack code which is used in your experiment?

@jiyongyu Would you mind sharing the last commit in gem5 that the STT project develops ontop of?

The original README in this repo was changed to README.md. But it cannot be resolved since the suffix may not be supported.